Debugging a link

This page walks through the usual questions about a front-panel link that is down, flapping or dropping packets: is there a signal, does the receiver lock, how open is the eye, what is the bit error rate, and do both ends agree on FEC and speed. It also shows how to change the transmit FIR taps, the FEC mode and the speed from the shell.

Every port on a Trident 3 is one or more lanes of an on-chip SerDes, so all of this is done with phy, portmod, ps and port. Reading is safe on a running switch. Every change on this page is made behind SONiC’s back: note the original value first, put it back when you are done, and expect a syncd restart to undo anything you leave.

Warning

Port names in the shell depend on port speeds: 100G ports are named ce, 10G and 40G ports xe and 1G ports ge, each numbered in port order. When a port changes speed class, it and the later ports of both classes are renamed (see Speed). Use port numbers, as printed in brackets by ps, in anything that changes speed or that you script.

The examples use a 100G link between two Trident 3 switches (ce27 on one, ce29 on the other, CWDM4 optics) and a 10G breakout lane on a copper DAC (xe3).

Is the port up?

Start with ps and the full port status:

Hardware-validated

drivshell> ps ce27-ce29,xe0-xe3
                 ena/        speed/ link auto    STP                  lrn  inter   max   cut   loop
           port  link  Lns   duplex scan neg?   state   pause  discrd ops   face frame  thru?  back   encap
      ce27(115)  up     4  100G  FD   SW  No   Forward         Untag    F    CR4  9122    No          IEEE
drivshell> port ce27
PORT: Status (* indicates PHY link up)
 *ce27    (EnabledLS(SW Forced((100GFD) Stad(e0:39:d7:88:3b:00) STP(Forward) Disc(untagged) Lrn(FWD) UtPri(0) Pfm(FloodNone) IF(CR4) PH(Slave) Max_frame(9122) MDIX(ForcedNormal, Normal) Medium(None) VLANFILTER(3)

* in front of the name means the PHY reports link. SW Forced(100GFD) is the configured speed with auto-negotiation off, IF(CR4) the interface type. A port that has no link and receives a fault from its partner, or none at all, also shows Fault(Local) or Fault(Remote).

Signal and lock: phy diag dsc

phy diag dsc prints the SerDes core state and one row per lane of the core, followed by a legend that explains each column. A healthy 100G port:

Hardware-validated — Lane rows of a healthy 100G link

drivshell> phy diag ce27 dsc
LN (CDRxN  , UC_CFG,UC_STS, RST, STP) SD LCK RXPPM CLK90 CLKP1 PF(M,L)  VGA DCO P1mV M1mV   DFE(1,2,3,4,5,6)      TXPPM TXEQ(n1,m,p1,2,3,rpara)    EYE(L,R,U,D)   LINK_TIME   BER
 0 (OSx1:x1, 0x0424, 0x00 , 0,0, 00 ) 1  1*   -1    29     0    ( 0,1)  12  -2  242  18 (  5,-15,  0,  0,  0,  1)    0   ( 8, 73,19, 0, 0, 0)   (234,296,151,155)    66.8
 1 (OSx1:x1, 0x0424, 0x00 , 0,0, 00 ) 1  1*   -1    28    -1    ( 0,1)  13 -12  240  14 (  2,-15,  0, -1,  0,  2)    0   ( 8, 73,19, 0, 0, 0)   (203,265,147,151)    65.6
 2 (OSx1:x1, 0x0424, 0x00 , 0,0, 00 ) 1  1*   -1    29     0    ( 0,1)  13   1  240  10 (  3,-15, -1,  3, -3,  3)    0   ( 8, 73,19, 0, 0, 0)   (250,328,153,165)    66.5
 3 (OSx1:x1, 0x0424, 0x00 , 0,0, 00 ) 1  1*   -1    28    -1    ( 0,1)  13   0  244   4 (  0,-15,  0,  0, -1,  0)    0   ( 8, 73,19, 0, 0, 0)   (250,312,159,165)    60.5

The columns that matter most:

SD

Signal detect: the receiver sees energy on the lane. 0 means no signal at all: no cable, no light, a module that is off, or a far end that is disabled.

LCK

The receiver’s clock and data recovery is locked to the incoming data.

PF, VGA, DFE

The receive equalizer: peaking filter, variable gain amplifier (0–37) and decision-feedback taps. A VGA at or near its maximum means the incoming signal is weak.

TXEQ(n1,m,p1,…)

This lane’s own transmit FIR taps: pre-cursor, main and post-cursor (see Transmit FIR taps).

EYE(L,R,U,D)

Eye margin at 1e-5 as seen by the receiver: left and right in mUI, up and down in mV. Small numbers mean a closed eye.

BER

Only filled in while the PRBS checker runs (see Bit error rate with PRBS).

With the far end disabled, every lane loses signal detect and lock and the eye collapses:

Hardware-validated — The same port with the far end shut down

drivshell> phy diag ce27 dsc
LN (CDRxN  , UC_CFG,UC_STS, RST, STP) SD LCK RXPPM CLK90 CLKP1 PF(M,L)  VGA DCO P1mV M1mV   DFE(1,2,3,4,5,6)      TXPPM TXEQ(n1,m,p1,2,3,rpara)    EYE(L,R,U,D)   LINK_TIME   BER
 0 (OSx1:x1, 0x0424, 0x00 , 0,0, 00 ) 0  0*    0    32     0    (10,0)  37  -3    0   0 (  7,  0,  0,  0,  0,  0)    0   ( 8, 73,19, 0, 0, 0)   (  0,  0,  0,  0)     0.0
 1 (OSx1:x1, 0x0424, 0x00 , 0,0, 00 ) 0  0*    0    32     0    (10,0)  37 -12    0   0 (  3,  0,  0,  0,  0,  0)    0   ( 8, 73,19, 0, 0, 0)   (  0,  0,  0,  0)     0.0
 2 (OSx1:x1, 0x0424, 0x00 , 0,0, 00 ) 0  0*    0    32     0    (10,0)  37   3    0   0 (  2,  0,  0,  0,  0,  0)    0   ( 8, 73,19, 0, 0, 0)   (  0,  0,  0,  0)     0.0
 3 (OSx1:x1, 0x0424, 0x00 , 0,0, 00 ) 0  0*    0    32     0    (10,0)  37   1    0   0 (  0,  0,  0,  0,  0,  0)    0   ( 8, 73,19, 0, 0, 0)   (  0,  0,  0,  0)     0.0

How to read the combinations:

• SD 0: nothing arrives. Check the cable or module, and that the far end is enabled and transmitting.

• SD 1, LCK 0: something arrives but the receiver cannot lock. The ends usually disagree on the lane speed, or the signal is too poor.

• SD 1, LCK 1 on every lane and still no link: the physical layer is fine and the problem is above it, typically a FEC or speed mismatch (see FEC).

phy diag … pcs prints a PCS status table, but on these switches its PCS LINK STAT column reads N even on ports that are up. Use ps and the dsc lane rows instead.

Eye diagram

portmod eyescan measures the receive eye of one lane and draws it. It takes the port number, not the name, and about 15 seconds per lane. Each character is the approximate error rate at that point as a power of ten: 7 means about 1e-7, 1 about 1e-1. The blank area in the middle is the open eye; the wider and taller it is, the more margin the link has.

Hardware-validated — Lane 0 of a healthy 100G CWDM4 link

drivshell> portmod eyescan port=115 mode=fast lane=0
 Timeout = 1000 ms
 Hmax    = 31
 Hmin    = -31
 Hstep   = 1
 Vmax    = 31
 Vmin    = -31
 Vstep   = 1
 mode    = 0
for u=0 p=115 lane_mask=1:



    +--------------------------------------------------------------------+
    | EYESCAN Phy: 0x1a9 lane_mask: 0x01                                 |
    +--------------------------------------------------------------------+

 Each character N represents approximate error rate 1e-N at that location
  UI/64  : -30  -25  -20  -15  -10  -5    0    5    10   15   20   25   30
         : -|----|----|----|----|----|----|----|----|----|----|----|----|-
   128mV : 111111111111111111111222233445677655433322222111111111111111111
   124mV : 111111111111111111111222334456677765543332222211111111111111111
   120mV : 1111111111111111111122223344567:  65544332222221111111111111111
   115mV : 1111111111111111111122233345667: 776554333222221111111111111111
   111mV : 111111111111111111112223344567 :   6654433322222111111111111111
   107mV : 111111111111111111122223345567 :   7655433322222111111111111111
   103mV : 111111111111111111122233345677-+---7665443332222211111111111111
    99mV : 11111111111111111122223344567  :    765544332222221111111111111
    95mV : 11111111111111111122223345667  :    776544333222221111111111111
    91mV : 11111111111111111122233445677  :    776554433222222111111111111
    86mV : 1111111111111111122223345567   :    :77655433322222111111111111
    82mV : 1111111111111111122233345677---+----+-7765443322222211111111111
    78mV : 111111111111111112223344567    :    :  765544332222211111111111
    74mV : 1111111111111111222233455677   :    : 7766544332222221111111111
    70mV : 11111111111111112223344567:    :    :  776554333222221111111111
    66mV : 11111111111111122223344567:    :    :   76654433322222111111111
    62mV : 1111111111111112222334566-+----+----+----7655443322222111111111
    57mV : 1111111111111112223344567 :    :    :    :665443332222211111111
    53mV : 1111111111111122223345567 :    :    :    :766544332222211111111
    49mV : 1111111111111122233345667 :    :    :    :766554333222221111111
    45mV : 111111111111122223344567  :    :    :    :776554333222221111111
    41mV : 11111111111112222334556---+----+----+----+-76654433222221111111
    37mV : 11111111111112223344566   :    :    :    :  7655433322222111111
    33mV : 11111111111122223344567   :    :    :    :  7665443322222111111
    28mV : 11111111111122233345667   :    :    :    :   765543332222211111
    24mV : 1111111111112223344567    :    :    :    :   776544332222211111
    20mV : 1111111111122223345567----+----+----+----+----76554333222211111
    16mV : 1111111111122233445677    :    :    :    :    76654433222211111
    12mV : 111111111112223344567:    :    :    :    :    77655433322221111
     8mV : 111111111112223345667:    :    :    :    :    :7765443322221111
     4mV : 11111111112223344567 :    :    :    :    :    :7765543322221111
     0mV : 11111111112223344567-+----+----+----+----+----+7765543322221111
    -4mV : 11111111112223344567 :    :    :    :    :    : 766543322221111
    -8mV : 11111111112223344567 :    :    :    :    :    :7765543322221111
   -12mV : 111111111112223345677:    :    :    :    :    :7765443322221111
   -16mV : 111111111112223344567:    :    :    :    :    77655433322221111
   -20mV : 111111111112223344567+----+----+----+----+----77654433222211111
   -24mV : 1111111111122223345567    :    :    :    :   776554333222211111
   -28mV : 1111111111112223344567    :    :    :    :   776544332222211111
   -33mV : 11111111111122233345667   :    :    :    :  7765543332222211111
   -37mV : 11111111111122223344567   :    :    :    :  7765443322222111111
   -41mV : 111111111111122233445677--+----+----+----+--7655433322222111111
   -45mV : 111111111111122223345567  :    :    :    :776654433222221111111
   -49mV : 111111111111112223344567  :    :    :    :776654433222221111111
   -53mV : 1111111111111122233345667 :    :    :    :776554333222221111111
   -57mV : 111111111111112222334456  :    :    :    :766544332222211111111
   -62mV : 1111111111111112223344567-+----+----+----7765443332222211111111
   -66mV : 11111111111111122223345567:    :    :    7655443322222111111111
   -70mV : 11111111111111112223344567:    :    :   77654433222222111111111
   -74mV : 11111111111111112223334567:    :    :   76554333222221111111111
   -78mV : 111111111111111122223345567    :    :  776544333222221111111111
   -82mV : 111111111111111112223344567----+----+-7766544332222211111111111
   -86mV : 111111111111111112223334566    :    :77765443322222211111111111
   -91mV : 1111111111111111122223345567   :    : 7655433322222111111111111
   -95mV : 11111111111111111122233445677  :    776654433222222111111111111
   -99mV : 11111111111111111122223345567  :    :76554333222221111111111111
  -103mV : 11111111111111111112223344567--+----+66544332222221111111111111
  -107mV : 111111111111111111122233345667 :   7665443322222211111111111111
  -111mV : 11111111111111111112222334556  :   7665443322222211111111111111
  -115mV : 111111111111111111112223344567 :  77654433322222111111111111111
  -120mV : 1111111111111111111122223345567:  76554333222221111111111111111
  -124mV : 11111111111111111111122233445677-776544332222221111111111111111
  -128mV : 111111111111111111111222333455677765543332222211111111111111111
         : -|----|----|----|----|----|----|----|----|----|----|----|----|-
  UI/64  : -30  -25  -20  -15  -10  -5    0    5    10   15   20   25   30

Scan each lane of the port in turn (lane=0 to lane=3 for a 4-lane port). mode=lowBER selects the slower low-BER scan. The EYE(L,R,U,D) column of dsc gives the same margins as four numbers when you only need a quick comparison.

Bit error rate with PRBS

A PRBS test replaces the traffic on a link with a pseudo-random pattern and counts the bit errors at the receiver. It stops all traffic on the port, so the link goes down for SONiC while it runs. Start the generator and checker on both ends with the same polynomial (p=3 is PRBS-31):

Hardware-validated — PRBS-31 on both ends, then read the checker

drivshell> phy diag ce27 prbs set p=3
drivshell> phy diag ce27 prbs get
ce27 (115):  PRBS has -2 errors!
drivshell> phy diag ce27 prbs get
ce27 (115):  PRBS OK!
drivshell> phy diag ce27 dsc
LN (CDRxN  , UC_CFG,UC_STS, RST, STP) SD LCK RXPPM CLK90 CLKP1 PF(M,L)  VGA DCO P1mV M1mV   DFE(1,2,3,4,5,6)      TXPPM TXEQ(n1,m,p1,2,3,rpara)    EYE(L,R,U,D)   LINK_TIME   BER
 0 (OSx1:x1, 0x0424, 0x00 , 0,0, 00 ) 1  1*   -1    29     0    ( 0,1)  11  -3  231  22 (  6,-15,  0,  0,  0,  1)    0   ( 8, 73,19, 0, 0, 0)   (218,296,140,144)    63.5   <1.2e-09
 1 (OSx1:x1, 0x0424, 0x00 , 0,0, 00 ) 1  1*   -2    28    -1    ( 0,1)  12 -11  231  12 (  2,-15,  0, -1,  0,  2)    0   ( 8, 73,19, 0, 0, 0)   (203,265,134,138)    61.5   <1.2e-09
 2 (OSx1:x1, 0x0424, 0x00 , 0,0, 00 ) 1  1*   -1    29     0    ( 0,1)  13   1  242  14 (  3,-15, -1,  3, -3,  3)    0   ( 8, 73,19, 0, 0, 0)   (234,312,153,159)    58.2   <1.2e-09
 3 (OSx1:x1, 0x0424, 0x00 , 0,0, 00 ) 1  1*   -1    28    -1    ( 0,1)  13   0  242   6 (  0,-15,  0,  0, -1,  0)    0   ( 8, 73,19, 0, 0, 0)   (234,296,157,155)    54.0   <1.2e-09

The first get right after set can report a negative count such as -2 errors; read it again. PRBS OK! means no errors since the last read. While PRBS runs, the BER column of dsc shows the measured bit error rate per lane, here better than 1.2e-9 on every lane.

Hardware-validated — The same on the far end

drivshell> phy diag ce29 prbs set p=3

Stop PRBS on both ends; the link comes back by itself:

Hardware-validated

drivshell> phy diag ce29 prbs clear
drivshell> phy diag ce27 prbs clear
drivshell> ps ce27
                 ena/        speed/ link auto    STP                  lrn  inter   max   cut   loop
           port  link  Lns   duplex scan neg?   state   pause  discrd ops   face frame  thru?  back   encap
      ce27(115)  up     4  100G  FD   SW  No   Forward         Untag    F    CR4  9122    No          IEEE

On Trident 3 the periodic statistics sub-commands are not available: phy diag … prbsstat and phy diag … fecstat answer PHY: Command not implemented, and phy diag … berproj answers Feature unavailable.

Hardware-validated

drivshell> phy diag ce27 fecstat start interval=2
PHY: Command not implemented

Failed to execute the diagnostic command. Error: Operation failed.
drivshell> phy diag ce27 berproj sample_time=5
Getting optimized threshold for all the lanes...
<nounit>:portmod_pm_phy_ber_proj: Feature unavailable
<nounit>:portmod_port_diag_ctrl: Feature unavailable

Failed to execute the diagnostic command. Error: Operation failed.

Transmit FIR taps

The transmitter pre-distorts the signal to make up for the loss of the channel. On Trident 3 SerDes it has a pre-cursor, a main and a post-cursor tap. phy control shows them as Preemphasis, packed as post << 16 | main << 8 | pre. For example 0x14410a is pre 10 (0x0a), main 65 (0x41) and post 20 (0x14), and dsc shows the same values as TXEQ(10, 65, 20, …).

Hardware-validated

drivshell> phy control xe3
Preemphasis              = 0x14410a
drivshell> phy diag xe3 dsc
LN (CDRxN  , UC_CFG,UC_STS, RST, STP) SD LCK RXPPM CLK90 CLKP1 PF(M,L)  VGA DCO P1mV M1mV   DFE(1,2,3,4,5,6)      TXPPM TXEQ(n1,m,p1,2,3,rpara)    EYE(L,R,U,D)   LINK_TIME   BER
 0 (OSx2:x2, 0x0400, 0x00 , 0,0, 00 ) 1  1   -30    32     0    ( 5,4)  32   3    0   0 (  0,  0,  0,  0,  0,  0)    0   ( 8, 70,22, 0, 0, 0)   (386,373,263,263)    43.6
 1 (OSx2:x2, 0x0400, 0x00 , 0,0, 00 ) 1  1   -30    32     0    ( 5,4)  32   3    0   0 (  0,  0,  0,  0,  0,  0)    0   (10, 65,20, 0, 0, 5)   (386,402,263,263)    36.8
 2 (OSx2:x2, 0x0400, 0x00 , 0,0, 00 ) 1  1   -30    32     0    ( 5,4)  32   9    0   0 (  0,  0,  0,  0,  0,  0)    0   (10, 65,20, 0, 0, 5)   (386,359,263,263)    31.7
 3 (OSx2:x2, 0x0400, 0x00 , 0,0, 00 ) 1  1   -30    32     0    ( 5,4)  32   2    0   0 (  0,  0,  0,  0,  0,  0)    0   (10, 65,20, 0, 0, 5)   (386,373,263,263)    42.5

The xe3 row is lane 3 of the core; the other rows belong to the other ports of the same core.

Setting Preemphasis changes all lanes of the port at once and takes effect immediately; the link stays up unless the new taps are too poor:

Hardware-validated

drivshell> phy control xe3 Preemphasis=0x002800
Current PHY control settings of xe3 ->
Preemphasis              = 0x2800
DriverCurrent            = 0xffffffff
DFE ENable               = False
LP DFE ENable            = False
BR DFE ENable            = False
LinkTraining Enable      = False
Interface                = 0xa
CL74                     = False
CL91                     = False
CL108                    = False

The effect is seen by the receiver at the other end, so judge a change by the far end’s dsc (VGA, DFE, eye) or eye scan, not by your own. On a 10G copper DAC, lowering only the main tap gave this at the far end:

Taps (pre, main, post)	Preemphasis	Far-end VGA	Far-end signal detect
10, 65, 20 (original)	0x14410a	26	yes
0, 40, 0	0x002800	30	yes
0, 20, 0	0x001400	37	yes
0, 10, 0	0x000a00	45 (saturated)	no, link down

With optical modules the host’s taps only drive the short electrical channel to the module, which re-times the signal. On a 100G CWDM4 link even a main tap of 20 with no pre- or post-cursor caused no errors at the far end’s PRBS checker. Tune taps on copper DAC and backplane links; on optical links look at the module instead.

Put the original value back when you are done (phy control xe3 Preemphasis=0x14410a). On SONiC the taps are normally programmed from the platform’s media settings when a module is inserted, so they may also be reset when a module is re-seated.

FEC

phy control also shows which FEC is enabled: CL74 (BASE-R FEC), CL91 (RS-FEC, the usual one for 100G) and CL108 (RS-FEC for 25G lanes). Change it with the same command:

Hardware-validated — RS-FEC on, then turned off on one end

drivshell> phy control ce27
CL74                     = False
CL91                     = True
CL108                    = False
drivshell> phy control ce27 CL91=False
CL91                     = False

Both ends must use the same FEC. With RS-FEC off on one end only, the link goes down on both ends, while the SerDes still shows signal and lock on every lane and an open eye. That combination, PMD fine but no link, is the sign of a FEC (or PCS) mismatch:

Hardware-validated — FEC mismatch

drivshell> ps ce27
                 ena/        speed/ link auto    STP                  lrn  inter   max   cut   loop
           port  link  Lns   duplex scan neg?   state   pause  discrd ops   face frame  thru?  back   encap
      ce27(115)  down   4  100G  FD   SW  No   Forward         Untag    F    CR4  9122    No          IEEE
drivshell> phy diag ce27 dsc
LN (CDRxN  , UC_CFG,UC_STS, RST, STP) SD LCK RXPPM CLK90 CLKP1 PF(M,L)  VGA DCO P1mV M1mV   DFE(1,2,3,4,5,6)      TXPPM TXEQ(n1,m,p1,2,3,rpara)    EYE(L,R,U,D)   LINK_TIME   BER
 0 (OSx1:x1, 0x0424, 0x00 , 0,0, 00 ) 1  1*    0    28     0    ( 0,1)  11  -3  236  20 (  3,-15,  0,  0,  0,  1)    0   ( 8, 73,19, 0, 0, 0)   (203,296,144,147)    68.2
 1 (OSx1:x1, 0x0424, 0x00 , 0,0, 00 ) 1  1*   -1    28    -1    ( 0,1)  12 -11  238   4 (  0,-14,  0, -1,  0,  1)    0   ( 8, 73,19, 0, 0, 0)   (218,265,140,149)    62.6
 2 (OSx1:x1, 0x0424, 0x00 , 0,0, 00 ) 1  1*   -1    30     0    ( 0,1)  12   3  231  12 (  5,-15, -1,  3, -3,  3)    0   ( 8, 73,19, 0, 0, 0)   (234,328,147,151)    67.9
 3 (OSx1:x1, 0x0424, 0x00 , 0,0, 00 ) 1  1*   -1    28    -1    ( 0,1)  13   0  244   2 (  0,-15,  0,  0, -1,  0)    0   ( 8, 73,19, 0, 0, 0)   (234,296,165,161)    63.1

Hardware-validated — The far end at the same time

drivshell> ps ce29
                 ena/        speed/ link auto    STP                  lrn  inter   max   cut   loop
           port  link  Lns   duplex scan neg?   state   pause  discrd ops   face frame  thru?  back   encap
      ce29(123)  down   4  100G  FD   SW  No   Forward         Untag    F  CAUI4  9122    No          IEEE

Turned off on both ends, the link comes up again without FEC:

Hardware-validated

drivshell> phy control ce27 CL91=False
CL91                     = False
drivshell> phy control ce29 CL91=False
CL91                     = False
drivshell> ps ce27
                 ena/        speed/ link auto    STP                  lrn  inter   max   cut   loop
           port  link  Lns   duplex scan neg?   state   pause  discrd ops   face frame  thru?  back   encap
      ce27(115)  up     4  100G  FD   SW  No   Forward         Untag    F    CR4  9122    No          IEEE
drivshell> ps ce29
                 ena/        speed/ link auto    STP                  lrn  inter   max   cut   loop
           port  link  Lns   duplex scan neg?   state   pause  discrd ops   face frame  thru?  back   encap
      ce29(123)  up     4  100G  FD   SW  No   Forward         Untag    F  CAUI4  9122    No          IEEE

Running without FEC only makes sense on a very clean link; check the receive error counters (show counters changed <port>, CLMIB_RFCS) afterwards.

Speed

port <port> speed=<Mb/s> forces a new speed. Both ends must match, and the cable or module must support it; a 100G CWDM4 module, for example, only runs at 100G.

Changing the speed class renames ports. Setting port 1 (ce0) to 40G turned it into xe0 and shifted every other name:

Hardware-validated — Port names after setting port 1 to 40G

drivshell> port ce0 speed=40000
drivshell> ps 1-13
                 ena/        speed/ link auto    STP                  lrn  inter   max   cut   loop
           port  link  Lns   duplex scan neg?   state   pause  discrd ops   face frame  thru?  back   encap
       xe0(  1)  !ena   4   40G  FD   SW  No   Forward  TX RX  Untag    F  XLAUI  9122    No          IEEE
       ce0(  5)  !ena   4  100G  FD   SW  No   Forward         Untag    F    CR4  9122    No          IEEE
       xe1(  9)  up     1   10G  FD   SW  No   Forward         Untag    F    XFI  9122    No          IEEE
       xe2( 10)  up     1   10G  FD   SW  No   Forward         Untag    F    XFI  9122    No          IEEE
       xe3( 11)  up     1   10G  FD   SW  No   Forward         Untag    F    XFI  9122    No          IEEE
       xe4( 12)  up     1   10G  FD   SW  No   Forward          None    F    XFI  9122    No          IEEE
       ce1( 13)  !ena   4  100G  FD   SW  No   Forward         Untag    F    CR4  9122    No          IEEE

Before the change, ports 1, 5, 9–12 and 13 were ce0, ce1, xe0–xe3 and ce2. Address the port by number to change it back. The speed change also changed the interface type and enabled pause, and setting the speed back did not undo that, so compare ps with what you noted before and set those explicitly:

Hardware-validated

drivshell> port 1 speed=100000
drivshell> ps 1-13
                 ena/        speed/ link auto    STP                  lrn  inter   max   cut   loop
           port  link  Lns   duplex scan neg?   state   pause  discrd ops   face frame  thru?  back   encap
       ce0(  1)  !ena   4  100G  FD   SW  No   Forward  TX RX  Untag    F  CAUI4  9122    No          IEEE
drivshell> port 1 if=CR4 TxPAUse=false RxPAUse=false
drivshell> ps 1
                 ena/        speed/ link auto    STP                  lrn  inter   max   cut   loop
           port  link  Lns   duplex scan neg?   state   pause  discrd ops   face frame  thru?  back   encap
       ce0(  1)  !ena   4  100G  FD   SW  No   Forward         Untag    F    CR4  9122    No          IEEE

Setting the interface type also reset the receive equalizer options (LP DFE) to their earlier values; check phy control too.

Putting it back

Before you leave the shell, compare each port you touched with the values you noted: ps (speed, interface, pause, link), phy control (taps, FEC, DFE) and, if PRBS ran, that prbs clear was given on both ends. SONiC does not see any of these changes and will not repair them; restarting syncd does, by re-initialising the ports from SONiC’s configuration, at the cost of a data-plane outage.