PHY

Set/Display phy characteristics

PHY

PHY and SerDes access: read and write PHY registers, list the PHY of each port, and run SerDes diagnostics (PRBS, eye scans, per-lane state, FEC and BER statistics). On Trident 3 every front-panel port is a lane of a Falcon (25G) or Merlin (10G) SerDes core, managed through PortMod (see PortMod). An external PHY exists only if the platform has one.

Sub-command keywords must be typed in full, in any case: phy diag works, phy dia does not. If the first word is not a keyword, the command treats it as a port bitmap and reads or writes PHY registers (see Register access below).

The built-in help does not list phymod, TS/TimeSync, extlb, wr, rd_cp, rd_cp2 or mod, and describes diag only in prose; the shell accepts all of them.

Several sub-commands are meant for older or external PHYs (WarpCore eye margins, BCM8483x manufacturing tests, BCM8747 clocks, EEE, OAM, long-reach copper, PHY firmware). On Trident 3 SerDes ports they usually just return an SDK error.

Reading (info, register reads, dumpall, the get forms and the diag display sub-commands) does not change anything, but each register access shares the MDIO/SBUS bus with linkscan. Writes, PRBS, loopback and the control options change SerDes or PHY state behind SONiC; PRBS and loopback stop traffic on the port, and a bad register write may leave the link down until the port is re-initialised.

Warning

phy diag takes the selected ports out of linkscan while it runs and puts them back afterwards. If a phy diag sub-command fails on a bad option, the ports may stay out of linkscan, and SONiC then no longer sees their link changes. Check with ps and re-enable linkscan on the ports if needed.

Warning

phy firmware writes a firmware image into an external PHY’s non-volatile memory and can leave the PHY unusable.

Hardware-validated

drivshell> phy info
Phy mapping dump:
      port   id0   id1  addr iaddr                    name           timeout
  ce0(  1)  600d  8770    81    81            TSCF-16/00/4     250000
  ce1(  5)  600d  8770    85    85            TSCF-16/01/4     250000
  xe0(  9)  600d  8770    89    89            TSCF-16/02/0     250000
  xe1( 10)  600d  8770    89    89            TSCF-16/02/1     250000
  xe2( 11)  600d  8770    89    89            TSCF-16/02/2     250000
  xe3( 12)  600d  8770    89    89            TSCF-16/02/3     250000
  ce2( 13)  600d  8770    8d    8d            TSCF-16/03/4     250000
  ce3( 17)  600d  8770    91    91            TSCF-16/04/4     250000
  ce4( 21)  600d  8770    95    95            TSCF-16/05/4     250000
  ce5( 25)  600d  8770    a1    a1            TSCF-16/06/4     250000
  ce6( 29)  600d  8770    a5    a5            TSCF-16/07/4     250000
  ce7( 33)  600d  8770    a9    a9            TSCF-16/08/4     250000
  ce8( 37)  600d  8770    ad    ad            TSCF-16/09/4     250000
  ce9( 41)  600d  8770    c1    c1            TSCF-16/10/4     250000
 ce10( 45)  600d  8770    c5    c5            TSCF-16/11/4     250000
 ce11( 49)  600d  8770    c9    c9            TSCF-16/12/4     250000
 ce12( 53)  600d  8770    cd    cd            TSCF-16/13/4     250000
 ce13( 57)  600d  8770    d1    d1            TSCF-16/14/4     250000
 ce14( 61)  600d  8770    d5    d5            TSCF-16/15/4     250000
  xe4( 66)  600d  8770   1c1   1c1            TSCE-16/00/0     250000
 ce15( 67)  600d  8770    e1    e1            TSCF-16/16/4     250000
 ce16( 71)  600d  8770    e5    e5            TSCF-16/17/4     250000
 ce17( 75)  600d  8770    e9    e9            TSCF-16/18/4     250000
 ce18( 79)  600d  8770    ed    ed            TSCF-16/19/4     250000
 ce19( 83)  600d  8770    f1    f1            TSCF-16/20/4     250000
 ce20( 87)  600d  8770    f5    f5            TSCF-16/21/4     250000
 ce21( 91)  600d  8770   181   181            TSCF-16/22/4     250000
 ce22( 95)  600d  8770   185   185            TSCF-16/23/4     250000
 ce23( 99)  600d  8770   189   189            TSCF-16/24/4     250000
 ce24(103)  600d  8770   18d   18d            TSCF-16/25/4     250000
 ce25(107)  600d  8770   1a1   1a1            TSCF-16/26/4     250000
 ce26(111)  600d  8770   1a5   1a5            TSCF-16/27/4     250000
 ce27(115)  600d  8770   1a9   1a9            TSCF-16/28/4     250000
 ce28(119)  600d  8770   1ad   1ad            TSCF-16/29/4     250000
 ce29(123)  600d  8770   1b1   1b1            TSCF-16/30/4     250000
 ce30(127)  600d  8770   1b5   1b5            TSCF-16/31/4     250000

phy info

List every port’s PHY: port name and number, the PHY ID registers (id0, id1), the external and internal MDIO addresses (addr, iaddr), the PHY driver name and the auto-negotiation timeout, under the heading Phy mapping dump:. Read-only.

Hardware-validated — Trident 3 with Falcon (TSC-F16) SerDes, abridged

drivshell> phy info
Phy mapping dump:
      port   id0   id1  addr iaddr                    name           timeout
  ce0(  1)  600d  8770    81    81            TSCF-16/00/4     250000
  ce1(  5)  600d  8770    85    85            TSCF-16/01/4     250000
  xe0(  9)  600d  8770    89    89            TSCF-16/02/0     250000
  xe1( 10)  600d  8770    89    89            TSCF-16/02/1     250000
  xe2( 11)  600d  8770    89    89            TSCF-16/02/2     250000
  xe3( 12)  600d  8770    89    89            TSCF-16/02/3     250000
  ce2( 13)  600d  8770    8d    8d            TSCF-16/03/4     250000
  ce3( 17)  600d  8770    91    91            TSCF-16/04/4     250000
  ce4( 21)  600d  8770    95    95            TSCF-16/05/4     250000
  ce5( 25)  600d  8770    a1    a1            TSCF-16/06/4     250000
  ce6( 29)  600d  8770    a5    a5            TSCF-16/07/4     250000
  ce7( 33)  600d  8770    a9    a9            TSCF-16/08/4     250000
  ce8( 37)  600d  8770    ad    ad            TSCF-16/09/4     250000
  ce9( 41)  600d  8770    c1    c1            TSCF-16/10/4     250000
 ce10( 45)  600d  8770    c5    c5            TSCF-16/11/4     250000
 ce11( 49)  600d  8770    c9    c9            TSCF-16/12/4     250000
 ce12( 53)  600d  8770    cd    cd            TSCF-16/13/4     250000
 ce13( 57)  600d  8770    d1    d1            TSCF-16/14/4     250000
 ce14( 61)  600d  8770    d5    d5            TSCF-16/15/4     250000
  xe4( 66)  600d  8770   1c1   1c1            TSCE-16/00/0     250000
 ce15( 67)  600d  8770    e1    e1            TSCF-16/16/4     250000
 ce16( 71)  600d  8770    e5    e5            TSCF-16/17/4     250000
 ce17( 75)  600d  8770    e9    e9            TSCF-16/18/4     250000
 ce18( 79)  600d  8770    ed    ed            TSCF-16/19/4     250000
 ce19( 83)  600d  8770    f1    f1            TSCF-16/20/4     250000
 ce20( 87)  600d  8770    f5    f5            TSCF-16/21/4     250000
 ce21( 91)  600d  8770   181   181            TSCF-16/22/4     250000
 ce22( 95)  600d  8770   185   185            TSCF-16/23/4     250000
 ce23( 99)  600d  8770   189   189            TSCF-16/24/4     250000
 ce24(103)  600d  8770   18d   18d            TSCF-16/25/4     250000
 ce25(107)  600d  8770   1a1   1a1            TSCF-16/26/4     250000
 ce26(111)  600d  8770   1a5   1a5            TSCF-16/27/4     250000
 ce27(115)  600d  8770   1a9   1a9            TSCF-16/28/4     250000
 ce28(119)  600d  8770   1ad   1ad            TSCF-16/29/4     250000
 ce29(123)  600d  8770   1b1   1b1            TSCF-16/30/4     250000
 ce30(127)  600d  8770   1b5   1b5            TSCF-16/31/4     250000

The output above is from a SONiC Trident 3 switch. Every ce port and the four split xe0–xe3 ports sit on TSCF-16 (Falcon16) cores, shown as TSCF-16/<core>/<n>, where <n> is 4 for a ce port and the lane (0–3) for a split port; the management port xe4 is on a TSCE-16 (Merlin) core. All rows show the same ID registers (600d 8770) and a 250000 µs timeout. Ports that share a core share an address (89 for xe0–xe3).

phy diag <pbmp> <sub_cmd> [<sub_cmd_args>]

Run a SerDes or PHY diagnostic on each port of the bitmap. Most sub-commands accept unit=<n> (0 is the internal SerDes, 1 the first external PHY) and if=<sys|line> to pick the PHY and its side. The sub-command word must be typed in full; an unknown word prints Error: unrecognized PHY DIAG command: <word>. See the warning above about linkscan.

The built-in help shows only dsc, veye, heye_r, heye_l, loopback, prbs, prbsstat, fecstat, linkmon, mfg and berproj; the shell also accepts peek, poke, load_uc, veye_u, veye_d, pcs, reg, eyescan, state, feyescan and sw_an.

phy diag sub-commands

Sub-command	Arguments	Purpose
dsc	[<arg>] [unit=<n>] [if=<sys|line>]. The optional word is passed to the SerDes driver; the help example uses debug.	Per-lane state: signal detect, lock, equalizer, eye.
pcs	[<arg>] [unit=<n>] [if=<sys|line>]	PCS status.
prbs	set|get|clear [unit=<n>] [if=<sys|line>] [Polynomial=<p>] [Invert=<n>]. Polynomial is P7(0), P15(1), P23(2), P31(3), P9(4), P11(5), P58(6), P49(7), P20(8), P13(9) or P10(10).	PRBS generator and checker. set and clear stop traffic.
prbsstat	[STArt [Interval=<sec>] | STOp | Counters | Ber | CLear | ?]	Periodic PRBS error counting and BER. PRBS must already be running. start runs a background collector until stop.
fecstat	same as prbsstat. The counters are CORREC_RS_CW, UNCORREC_RS_CW, BITS_ERROR, RS_SYMBOL_ERR, CORREC_BASER and UNCORREC_BASER.	Periodic FEC counters and pre-FEC BER.
berproj	[unit=<n>] [if=<sys|line>] [hist_errcnt_threshold=<n>] [sample_time=<n>]	Post-FEC BER projection.
eyescan	type, vertical_max, vertical_min, horizontal_max, horizontal_min, sample_resolution, sample_time, counter, flags, lane, error_threshold, time_upper_bound, nof_threshold_links, unit, if, ber_scan_mode, timer_control, max_err_control	Eye scan. See also portmod eyescan.
feyescan	[unit=<n>] [if=<sys|line>] [lane=<n>]	Fast eye scan.
LoopBack	[unit=<n>] [InterFace=<sys|line>] mode=<remote|local|global|none>	Set PHY loopback. Stops normal traffic.
linkmon	set|get [unit=<n>] [if=<sys|line>] [lane=<n>] [mode=<0..8>]	PCS link monitor.
reg	[core0|core1|core2|mld] <aer> <reg> [<value>]	Read, or with a value write, a SerDes register.
peek, poke	fb=<n> lane=<n> / fb=<n> val=<n>	Internal SerDes register peek and poke. poke writes.
load_uc	crc=<n> debug=<n>	Reload SerDes microcode. Disrupts the link.
veye, veye_u, veye_d, heye_r, heye_l	live, BER, range, lane, time_upper_bound	WarpCore eye margins (not Trident 3 SerDes).
mfg, state	Test=<n> Data=<n> File=<file>	BCM8483x copper-PHY tests and state dumps (not Trident 3).
sw_an	none	Software auto-negotiation diagnostics; see SW_AN.

Hardware-validated

drivshell> phy diag xe0 dsc
 tscf16_phy_pmd_info_dump:539 type = 16384 laneMask  = 0x1, Address = 0x89
SerDes type = falcon16_tsc
CORE RST_ST  PLL_PWDN  UC_ATV   COM_CLK   UCODE_VER  API_VER  AFE_VER   LIVE_TEMP   AVG_TMON   RESCAL   VCO_RATE  ANA_VCO_RANGE  REFCLK_2x  PLL_DIV  PLL_LOCK PLL_COMP_THRESH
 00   0,00      0        1     156.25MHz   D103_18   A10731     0xc0       41C      (16) 42C    0x08    20.625GHz     209            0       132        1         -200mV

**************************************************************************************************************
****                          Legend of Entries in display_core_state()                                   ****
**************************************************************************************************************
*  RST_ST           : Core DP Reset State{reset_active, reset_occured, reset_held}, Core uC Status byte(hex) *
*  PLL_PWDN         : PLL Powerdown Control Bit (active high)                                                *
*  UC_ATV           : UC Active bit                                                                          *
*  COM_CLK          : COM Clock frequency in MHz                                                             *
*  UCODE_VER        : Microcode Version [majorversion_minorversion]                                          *
*  API_VER          : API Version                                                                            *
*  AFE_VER          : AFE Hardware Version                                                                   *
*  LIVE_TEMP        : Live Die temperature in Celsius                                                        *
*  AVG_TMON         : uC Temp_idx, Average temperature in Celsius                                            *
*  RESCAL           : Analog Resistor Calibration value                                                      *
*  VCO_RATE         : uC VCO Rate in GHz (approximate)                                                       *
*  ANA_VCO_RANGE    : Analog VCO Range                                                                       *
*  REFCLK_2x        : Refclk doubler enabler                                                                 *
*  PLL_DIV          : (Register Value) Actual PLL Divider Value                                              *
*  PLL_Lock         : PLL Lock                                                                               *
**************************************************************************************************************
LN (CDRxN  , UC_CFG,UC_STS, RST, STP) SD LCK RXPPM CLK90 CLKP1 PF(M,L)  VGA DCO P1mV M1mV   DFE(1,2,3,4,5,6)      TXPPM TXEQ(n1,m,p1,2,3,rpara)    EYE(L,R,U,D)   LINK_TIME   BER
 0 (OSx2:x2, 0x0400, 0x00 , 0,0, 00 ) 1  1*  -30    32     0    ( 5,4)  32   4    0   0 (  0,  0,  0,  0,  0,  0)    0   ( 8, 70,22, 0, 0, 0)   (386,388,263,263)    43.6
 1 (OSx2:x2, 0x0400, 0x00 , 0,0, 00 ) 1  1*  -30    32     0    ( 5,4)  32   4    0   0 (  0,  0,  0,  0,  0,  0)    0   (10, 65,20, 0, 0, 5)   (386,402,263,263)    36.8
 2 (OSx2:x2, 0x0400, 0x00 , 0,0, 00 ) 1  1*  -30    31     0    ( 5,4)  32  10    0   0 (  0,  0,  0,  0,  0,  0)    0   (10, 65,20, 0, 0, 5)   (386,373,263,263)    31.7
 3 (OSx2:x2, 0x0400, 0x00 , 0,0, 00 ) 1  1*  -30    32     0    ( 5,4)  32   1    0   0 (  0,  0,  0,  0,  0,  0)    0   (10, 65,20, 0, 0, 5)   (359,402,263,263)    42.5

...

On a Trident 3 dsc prints the core state of the Falcon16 core (SerDes type = falcon16_tsc, microcode version, live die temperature, VCO rate, PLL lock), a legend, then one row per lane of the core, not only the lanes of the port (all four lanes for xe0), and a second legend. About 60 lines per port. The BER column stays empty unless the PRBS checker runs.

Unvalidated — PRBS-31 on the internal SerDes, then read the checker (stops traffic)

drivshell> phy diag xe0 prbs set unit=0 p=3
drivshell> phy diag xe0 prbs get unit=0
drivshell> phy diag xe0 prbs clear unit=0

Unvalidated — BER from running PRBS

drivshell> phy diag xe0 prbsstat start i=60
drivshell> phy diag xe0 prbsstat ber
drivshell> phy diag xe0 prbsstat stop

Unvalidated — Post-FEC BER projection

drivshell> phy diag xe0 berproj sample_time=80

PRBS testing on Broadcom (SONiC) — prbs_broadcom.md + README walks through the PRBS, prbsstat and berproj workflow on other Broadcom chips; some of these sub-commands may not be available on every chip.

phy prbs <pbmp> <set | get | clear> [Mode=<hc | si>] [Polynomial=<p>] [LoopBack=<bool>]

PRBS through the PHY-control interface. Mode is si (SerDes) or hc. Polynomial accepts P7(0) to P58(6) only; the phy diag … prbs form also accepts 7 to 10. set and clear stop traffic on the port; get reports the checker state.

Unvalidated

drivshell> phy prbs xe0 set Mode=si Polynomial=3

phy control <pbmp> [RxTune [<value>] | Dump | <key>=<value> ...]

With only a bitmap, show the PHY-control values of each port. With <key>=<value> options, set them. Keys include WanMode, Preemphasis, DriverCurrent, PreDriverCurrent, EqualizerBoost, Interface, InterfaceMax, SwRxLos, Dfe, LpDfe, BrDfe, LT, Cl74, Cl91, Cl108 and several Macsec* keys. RxTune starts receive-equalizer tuning (Rx Equalization Tuning start). Setting values changes SerDes state behind SONiC.

Hardware-validated — A 10G port on Trident 3, abridged

drivshell> phy control xe0
Current PHY control settings of xe0 ->
Preemphasis              = 0x164608
DriverCurrent            = 0xffffffff
DFE ENable               = False
LP DFE ENable            = False
BR DFE ENable            = False
LinkTraining Enable      = False
Interface                = 0xa
CL74                     = False
CL91                     = False
CL108                    = False

The output above is from a SONiC Trident 3 switch, for one of the 10G ports of a split 100G port: link training and the clause 74, 91 and 108 FEC settings are all off.

phy int <pbmp> [<regnum> [<value>]]

Like Register access below, but on the internal (intermediate) PHY of each port instead of the outermost one.

Unvalidated

drivshell> phy int xe0

Register access: phy <pbmp> [<regnum> [<value> | <devad> [<value>]]]

With only a bitmap, print the standard registers of each port’s PHY. With a register number, read that register; with a value as well, write it, which changes PHY state. For clause-45 PHYs the second number is the device address.

Unvalidated

drivshell> phy xe0 0x1

phy raw [c45 | sbus | sim] <mii_addr> [<devad>[.<lane>]] <regnum> [<value>[/<mask>]]

Read or write a register by raw MDIO address, without going through a port. c45, sbus and sim need a device address; only sbus and sim take a lane and a write mask. A write changes PHY state.

Unvalidated

drivshell> phy raw 0x81 0x2

phy dumpall <c22 | c45> [<start_addr> [<end_addr>]]

Scan MDIO addresses and print the PHY ID registers found, in a table headed PRTAD DEVAD REG. Read-only, but it touches every address on the bus.

Unvalidated

drivshell> phy dumpall c22

phy phymod [<pbmp> [<mask> [<lane>]] | addr [<addr> [<mask> [<lane>]]]]

Set the filter for the phymod register-access debug log: PHY address, access mask and lane. With a port bitmap the address is taken from the port’s internal PHY. The command prints the current filter as addr=0x<n> mask=0x<n> lane=<n>. Changes debug settings only.

Unvalidated

drivshell> phy phymod addr

phy wr <port> <block> <address> <value>

Write an internal SerDes register by block and address. <port> is a port number. Changes SerDes state.

Unvalidated

drivshell> phy wr 1 0x8000 0x10 0x0

phy rd_cp <port> <block> <address> <expected>

Read an internal SerDes register and compare it with an expected value. Prints Pass or Error: block <b>, register <r> expected <x>, got <y>. Read-only.

Unvalidated

drivshell> phy rd_cp 1 0x8000 0x10 0x0

phy rd_cp2 <port> <block> <address> <expected> <mask>

Like rd_cp, but compare only the bits set in <mask>. Read-only.

Unvalidated

drivshell> phy rd_cp2 1 0x8000 0x10 0x0 0xff

phy mod <port> <block> <address> <value> <mask>

Read-modify-write a PHY register: only the bits in <mask> are set to <value>. A negative block selects a direct address. Changes PHY state.

Unvalidated

drivshell> phy mod 1 0x8000 0x10 0x1 0x1

phy margin <pbmp> <maxget | valueget | valueset | set | clear> [marginval=<n>]

Transmit-margin control on PHYs that support it. maxget and valueget read; set, valueset and clear change the margin.

Unvalidated

drivshell> phy margin xe0 maxget

phy eee <pbmp> [MOde=<native | auto | none>] [LAtency=<variable | fixed>] [IDle_th=<0-7>] [STats=<get | clear>]

Energy-Efficient Ethernet mode, latency and counters on PHYs that support EEE. With only a bitmap the command shows the settings. STats=all is also accepted.

Unvalidated

drivshell> phy eee xe0 STats=get

phy power <pbmp> [mode=<auto_low | auto_down | auto_off | low | full>] [Sleep_Time=<n>] [Wake_Time=<n>]

PHY power-saving mode. Sleep_Time and Wake_Time apply only to auto_down. With only a bitmap the command shows the mode.

Unvalidated

drivshell> phy power xe0

phy longreach <pbmp> [SPeed=<n>] [PAirs=<n>] [GAin=<n>] [AutoNeg=<bool>] [LocalAbility=<abil>] [RemoteAbility=<abil>] [CurrentAbility=<abil>] [MAster=<bool>] [Active=<bool>] [ENable=<bool>]

Long-reach (BroadR-Reach) copper settings. The built-in help shows only [parameter=value]; the shell accepts the keys listed here. With only a bitmap the command shows the settings.

Unvalidated

drivshell> phy longreach xe0

phy extlb <pbmp> [ENable=<bool>]

Show or set external loopback on the PHY. Enabling it stops normal traffic.

Unvalidated

drivshell> phy extlb xe0

phy clock <pbmp> [PRImary=<bool>] [SECondary=<bool>] [FRequency=<hz>] [AutoDisable=<bool>] [AutoSECondary=<bool>] [ClockSource=<n>] [BAse=<n>] [OFfset=<n>]

Recovered-clock outputs of PHYs that have them (the help mentions BCM8747). The built-in help shows only PRImary, SECondary and FRequency; the shell also accepts AutoDisable, AutoSECondary, ClockSource, BAse and OFfset.

Unvalidated

drivshell> phy clock xe0

phy oam <pbmp> [MODE=<y1731 | bhh | ietf>] [DIR=<tx | rx>] [MacCheck=<bool>] [ControlWord=<bool>] [ENTROPY=<bool>] [TimeStampFormat=<ntp | ptp>] [ETHerType=<n>] [MACIndex=<1-3>] [MACAddrHi=<n>] [MACAddrLow=<n>] ...

OAM timestamping in PHYs that support it. The shell also accepts ControlWord, which the built-in help does not show.

Unvalidated

drivshell> phy oam xe0

phy TimeSync <pbmp> [ENable=<bool>] [CaptureTS=<bool>] [HeartbeatTS=<bool>] ... [LoadAll=<bool>] [FrameSync=<bool>] [InBand...=<value>]

Show or set IEEE 1588 timestamping in a 1588-capable PHY. TS is a synonym. About 40 options are accepted, from ENable, CaptureTS and HeartbeatTS through the Tx…/Rx… message modes, GMode, FramesyncMode, SyncoutMode and LoadAll to the InBand… options.

Unvalidated

drivshell> phy TimeSync xe0

phy firmware <port> set=<filename> [-y] [int] [raw]

Write a firmware image to an external PHY’s non-volatile memory. Give one port only. -y skips the confirmation prompt. The shell also accepts int and raw, which the built-in help does not show. Trident 3 SerDes ports have no such memory; see the warning above.

Unvalidated

drivshell> phy firmware xe0 set=/tmp/phy.bin

Built-in help

Parameters: [int] <ports> [regnum [value/devad] [value]]
            raw [c45|sbus|sim] <mii-addr> [devad[.lane]] <regnum> [<value>[/<mask>]]
            dumpall <c22|c45> [start_phy_addr [end_phy_addr]]
            info
            control <ports> [phy_control_type=value]
            firmware <port> set=<filename> [-y]
            eee <port> [mode=<native|auto|none>|latency=<variable|fixed>|
                        stats=<get|clear>|idle_th=<0-7>
            power <ports> [mode=mode_type [sleep_time=value] [wake_time=value]]
            longreach   <ports> [parameter=value]
            prbs <ports> set|get|clear Mode=<hc|si> [Polynomial=<value>]
                         [LoopBack=true|false]
            clock <ports> [PRImary=<t|f>] [SECondary=<t|f>]
                          [FRequency=<125000|195312|156250> for BCM8747]
            margin <ports> maxget|valueget|valueset|set|clear [marginval=<value>]
            oam <ports> [MODE={y1731|bhh|ietf}] [DIR={tx|rx}]
                        [MacCheck={yes|no}] [ENTROPY={yes|no}]
                        [TimeStampFormat={ntp|ptp}] [ETHerType=<value>]
                        [MACIndex={1|2|3}] [MACAddrHi=<value[47:32]]
                        [MACAddrLow=<value[31:0]>]
                        [MACAddrHi1=<value[47:32]>] [MACAddrLow1=<value[31:0]>]
                        [MACAddrHi2=<value[47:32]>] [MACAddrLow2=<value[31:0]>]
                        [MACAddrHi3=<value[47:32]>] [MACAddrLow3=<value[31:0]>]
    Set or display PHY registers.  If only <ports> is specified,
    then registers for those ports' PHYs are displayed. <ports> is a
    standard port bitmap, e.g. fe for all 10/100 ports, fe5-fe7 for
    three FE's, etc. (see "help pbmp").  If the int option is given,
    the intermediate PHY for the port is used instead of the outer PHY.
    In 'raw' mode, the direct mii-address can be specified. 'c45', 'sbus'
    and 'sim' raw modes require a devad parameter, and only 'sbus' and 'sim'
    raw modes support optional lane and mask.
    dumpall <c22|c45> - Do a clause 22 or clause 45 PHY scan of ID registers
    info    - display PHY device ID and attached PHY drivers
    firmware - program the firmware given by the filename to the PHY
               device's non-volatile storage. The file must be in binary
               format.
    eee      - set or display eee mode, latency and counters for PHYs devices
               implementing EEE. Mode can be native or auto. Latency may be
               variable or fixed. idle_th may be a value from 0 to 7.
    power    - set or display power mode for the PHY devices implemented
               power control. mode_type has these values: auto_low,
               auto_down,auto_off,low and full. sleep_time and wake_time
               only applies to auto_down power mode
    control - set or display PHY settings such as WAN, Preemphasis, etc.,
    longreach - set or display PHY longreach settings.

    diag - phy diagnostic commands.
    phy diag <pbm> <sub_cmd> [sub cmd parameters]
     All sub commands take two general parameters: unit and if. This identifies
     the instance the command targets to.
    unit = 0,1, ....
       unit takes numeric values identifying the instance of the PHY devices
       associated with the given port. A value 0 indicates the internal
       PHY(serdes) the one directly connected to the MAC. A value 1 indicates
       the first external PHY.
    if(interface) = [sys | line]
       interface identifies the system side interface or line side interface of
       PHY device.
    The list of sub commands:
       dsc - display lane information, include sigdet, lock etc.
              Example:
                BCM.0> phy diag ce0 dsc debug u=0 if=line
                BCM.0> phy diag ce0 dsc debug u=1 if=sys
       veye - vertical eye margin mesurement. WC only. All eye margin functions
              are used in conjunction with PRBS utility in the configed speed mode
       heye_r - right horizontal eye margin mesurement. WC only
       heye_l - right horizontal eye margin mesurement. WC only
       for the WarpLite, there are three additional parameters, live link or not,
       par1 for the target BER value for example: -18 stands for 10^(-18)
       par2 will be percentage range for example, 5 means checxk for +-%5 of the target BER
       loopback - put the device in the given loopback mode
                  parameter: mode=[remote | local | none]
       prbs - perform various PRBS functions. Takes all parameters of the
              "phy prbs" command except the mode parameter.
              Example:
                A port has a WC serdes and 84740 PHY connected. A typical usage
                is to use the PRBS to check the link between WC and the system
                side of the 84740. Use port xe0 as an example:
                BCM.0> phy diag xe0 prbs set unit=0 p=3
                BCM.0> phy diag xe0 prbs set unit=1 if=sys p=3
                BCM.0> phy diag xe0 prbs get unit=1 if=sys
                BCM.0> phy diag xe0 prbs get unit=0
       prbsstat - periodically collect PRBS error counters and
              compute BER based on the port configuration and
              the observed error counters.
              prbsstat assumes PRBS is already running on the ports
              that prbsstat will be monitoring.
              Parameters:
                 [STArt [Interval=<secs>]]
                 [STOp]
                 [Counters]
                 [Ber]
                 [Clear]
              Example:
                BCM.0> phy diag cd0-cd3 prbsstat ?
                BCM.0> phy diag cd0-cd3 prbsstat
                BCM.0> phy diag cd0-cd3 prbsstat start i=60
                BCM.0> phy diag cd0-cd3 prbsstat counters
                BCM.0> phy diag cd0-cd3 prbsstat ber
                BCM.0> phy diag cd0-cd3 prbsstat clear
                BCM.0> phy diag cd0-cd3 prbsstat stop
       fecstat - periodically collects FEC status counters such as
              corrected and uncorrected FEC codewords, symbols error and
              and bits error for a given port.
              The command then uses the bits error count to compute pre-FEC
              bit error rate for the port, and uses symbols error count to
              compute the symbol error rate for each lane of the port.
              Parameters:
                 [STArt [Interval=<secs>]]
                 [STOp]
                 [Counters]
                 [Ber]
                 [Clear]
              Example:
                BCM.0> phy diag cd0-cd3 fecstat ?
                BCM.0> phy diag cd0-cd3 fecstat
                BCM.0> phy diag cd0-cd3 fecstat start i=10
                BCM.0> phy diag cd0-cd3 fecstat counters
                BCM.0> phy diag cd0-cd3 fecstat ber
                BCM.0> phy diag cd0-cd3 fecstat clear
                BCM.0> phy diag cd0-cd3 fecstat stop
       linkmon - perform various PCS linkmonitor functions. Takes following parameters
                unit, interface side(line/sys), lane(lane number if 0xf enable linkmon
                on the lane of a port), mode (link mon mode: 0:LMM OFF, 1: LMM_PCS49_1X10G,
                2: LMM_PCS82_4X10G, 3: LMM_PCS82_2X25G, 4: LMM_PCS82_4X25G, 5: LMM_FC4,
                6: LMM_FC8, 7: LMM_FC16, 8: LMM_FC32,
              Example:
                A typical usage of link monitor to check PCS link between TSCF and
                the system side of the 82381. Use port ce0 as an example:
                BCM.0> phy diag ce0 linkmon set u=1 if=line lane=1 mode=4
                BCM.0> phy diag ce0 linkmon get u=1 if=line lane=1
                BCM.0> phy diag ce0 linkmon set u=1 if=line lane=1 mode=0
       mfg - run manufacturing test on PHY BCM8483X
                  parameter: (t)est=num (d)ata=<val> (f)ile=filename
                  Test should be :
                  1 (HYB_CANC), needs (f)ile=filename
                  2 (DENC),     needs (f)ile=filename
                  3 (TX_ON)     needs (d)ata = bit map for turning TX off on pairs DCBA
                  0 (EXIT)
      berproj - Post FEC BER projection. Takes following parameters
                berproj [hist_errcnt_threshold=<value>] [sample_time=<value>]
                Example:
                BCM.0> phy diag cd0 berproj
                BCM.0> phy diag cd0 berproj sample_time=80
                BCM.0> phy diag cd0 berproj hist_errcnt_threshold=4
    prbs     - set, get, or clear internal PRBS generator/checker.

Further reading

bcmsh.md (published as https://kamelnetworks.github.io/sonic/bcmsh.html), OpenBCM sdk-6.5.27/rc: rc.soc, config.bcm, td3_sanity.soc, cmd_td3_tr514_lr.soc, tr51/tr517_bcm56870_a0.soc, bcm_diag_info.soc …, SDK-6.5.20..6.5.27 Resolved-Issues-Improvements.xlsx (7 files), cPCI-6S10 Series 6U CompactPCI Switch Blade User’s Manual (50-15099-1000, Rev 1.0), Cisco Nexus 9000 Series NX-OS Troubleshooting Guide, Release 9.3(x) – Troubleshooting VLANs, BISDN Linux docs: OF-DPA client tools, auto-negotiation, FEC, SwitchControl, known issues, bcm cli 命令, BCM_SDK命令, bcm cmd, bcm 使用技巧, PRBS testing on Broadcom (SONiC) — prbs_broadcom.md + README, Auto-MDIX / Flow Control wiki notes (Chinese), Edgecore AS5610-52X reverse engineering: Cumulus 2.5 baseline captures.