PHY

A command of the separate bcma command line; see Commands for other chip families.

PHY based commands.

PHY info [<port>|<port-range>]
<port> list [raw] <reg-name>
<port>|<port-range> [raw] <reg-expr> [<val>|<field>=<val> ...]
<port>|<port-range> <addr-expr> [<val>]
raw [pm]<pm-id> <addr-expr> [<val>]
event_log_mask <port> [<val>]
diag ...
diag <port> deskew
debug set acc_rd [serdes_addr]
debug set acc_wr [serdes_addr]
debug clear
diag <port> cdr set cdr_mode=br lane=1
diag <port> cdr clear
diag <port> cdr get lane=0
ucram <port> list
ucram <port> <ucram_id-expr> [<val>]
diag <port> tx_taps get lane=1
diag <port> tx_taps set nlc_%=3 nlc_low_%=-4 pre3=0 pre2=0 pre1=-1 main=120 post1=0 post2=1 post3=0 lane=<val>

Built-in help

<reg-expr> := <reg>[.<lane-index>][.<pll-index>]
<addr-expr> := <addr>[.<lane-index>][.<pll-index>]
<ucram_id_expr> := <ucram_id[.<lane-index>]

List or read/write internal PHY registers.
This command takes the logical port as the port number domain.
If <lane-index> is specified, it will override the default lane index
of the associate port. If value 1 is prefix before register address,
it will access the register of specified devad device. If <pll-index>
is specified, it will override the default register pll index.
Raw register command takes the port macro (PM) ID (starting with 1)
and register address as input to access registers of the PM in
an early stage before the underlying driver is attached.
event_log_mask set/get uC RAM variable usr_event_log_group_mask.

The syntax for "phy diag" is identical to the "phydiag" command.
Use "help phydiag" to see the detailed help text.
ucram command accesses PMD uC RAM user's variables. ucram takes logical
port and the ID of ucram list.
"tx_taps" is to set TXFIR tap values and adjust them based on
upper and lower eye non linear compensation(nlc).
nlc_% (upper_eye nlc) and nlc_low_% (lower_eye nlc) are independent.
"tx_taps" includes the following arguments:
pre3, pre2, pre1, main, post1 post2, post3, nlc_%, and nlc_low_%

Built-in examples

info 1
info 1-10
1 list PHYID
1 PHYID2r
1 0x1d147.0.1
1 0x9000.0
1,2,3 0xc050
1-5 sc_x4_control_control
raw pm1 0x9000
event_log_mask 1
event_log_mask 1 0xE0FFFF
debug set acc_wr 0x401
debug set acc_rd
debug clear
ucram 1 list
ucram 1 1
diag 1 tx_taps get lane=2
diag 1 tx_taps set nlc_%=3 nlc_low_%=-4 pre3=0 pre2=0 pre1=-1 main=120 post1=0 post2=1 post3=0 lane=0
diag 1 deskew