CPU, DMA, interrupts and counters
How the SDK talks to the chip over PCIe: packet and table DMA, S-channel, interrupts, counter collection and CPU threads.
Set in several SONiC Trident 3 HWSKU files: bcm_stat_flags, bcm_stat_interval, bcm_stat_jumbo, cdma_timeout_usec, ctr_evict_enable, dma_desc_timeout_usec, miim_intr_enable, pdma_descriptor_prefetch_enable, pktdma_poll_mode_channel_bitmap, schan_intr_enable, tdma_intr_enable, tdma_timeout_usec, tslam_timeout_usec.
- bcm_esw_pscan_thread_pri
- Type:
- number
Specifies the priority of the bcmPSCAN thread
- bcm_rx_thread_pri
- Type:
- number
Specifies the priority of the BCM RX thread
- bcm_stat_flags
- Type:
- number
Flag values to be ORd together: 0x0 indicates that counter DMA should NOT be used 0x1 indicates that counter DMA should be used (default).
- SONiC:
set in 10 Trident 3 HWSKU files;
1,0
- bcm_stat_interval
- Type:
- number
Set stat collection interval in microseconds. Setting this to 0 will prevent counters from being started.
- SONiC:
set in 16 Trident 3 HWSKU files;
2000000,1000000
- bcm_stat_jumbo
- Type:
- number
- Default:
1518
Threshold value for oversize (*OVR) frame size. Values over 1518 affect the *OVR statistics computation
- SONiC:
set in 9 Trident 3 HWSKU files;
9236
- bcm_stat_pbmp
- Type:
- number
- Default:
0
BCM Statistics Collection: Set bitmap of ports on which stat collection will be enabled. Default is all ports.
- bcm_stat_sync_timeout
- Type:
- number
Timeout delay in microseconds before bcm_stat_sync returns BCM_E_TIMEOUT
- bcm_tx_queue_size
- Type:
- number
Specifies the maximum number of packets which can start to allocate resources and transmit. Depending on the Tx resources, an appropriate value can get better performance. The range of suggested values is 64 to 512. If fewer than 10 threads may transmit simultaneously, this parameter can be left at the default value of 0.
- bcm_tx_thread_pri
- Type:
- number
Specifies the priority of the BCM TX thread
- ccm_dma_enable
- Type:
- number
Enable/Disable CCM DMA
- ccmdma_intr_enable
- Type:
- number
- Default:
1
CCM DMA operation should use interrupt rather than poll for completion
- ccmdma_timeout_usec
- Type:
- number
CCM DMA operation timeout in microseconds
- cdma_timeout_usec
- Type:
- number
Counter DMA collection pass timeout in microseconds
- SONiC:
set in 24 Trident 3 HWSKU files;
3000000,15000000
- cmic_dma_abort_in_cold_boot
- Type:
- number
Abort all pending DMA operations in cold boot as early as possible.
- cmic_regtest_skip
- Type:
- number
- cmicm_dcb_error_mitigate_enable
- Type:
- number
Enable retry and DMA restart incase of DCB count mismatch in CMICM.
- cmicx_ls_hw_cfg_async_enable
- Type:
- number
Enable async communication when configuring m0 firmware based hardware linkscan.
- cmicx_schan_num_cfg_count
- Type:
- number
Count of CMICX SCHAN channels cofigured to be used in SDK.
- counter_collection_preempt_enable
- Type:
- number
Enable the counter collection preemption. Current counter collection will be preempted when the following APIs are active: - bcm_stat_sync_multi_get - bcm_stat_sync_multi_get32 Valid values: 0: Disable 1: Enable
- counter_collection_preempt_max_period_usec
- Type:
- number
The maximum time period in microseconds for counter collection preemption. When continous preemption time exceeds this maximum period, the preemption will be paused to allow a full counter collection completes Valid values: 0: No maximum period 1 ~ (2^31-1): 1 ~ 2,147,483,647 microseconds Note if this value is non-zero but less than current counter collection interval, the maximum preempt time period will be current counter collection interval,
- counter_thread_pri
- Type:
- number
Miscellaneous thread priorities; 0 is highest and 255 is lowest
- ctr_evict_dma_intr_enable
- Type:
- number
- Default:
1
- ctr_evict_enable
- Type:
- number
- Default:
1
- SONiC:
set in 4 Trident 3 HWSKU files;
0
- dma_abort_timeout_usec
- Type:
- number
timeout for DMA abort (of all DMA types) in microseconds
- dma_desc_intr_enable
- Type:
- number
- Default:
0
SBUSDMA descriptor mode operation should use interrupt rather than poll for completion
- dma_desc_timeout_usec
- Type:
- number
SBUSDMA descriptor mode operation timeout in microseconds
- SONiC:
set in 9 Trident 3 HWSKU files;
15000000
- dma_from_cache
- Type:
- number
- dma_mem_debug_enable
- Type:
- string
- fschan_enable
- Type:
- number
- Default:
0
Enable Fast SCHAN present in CMICm
- host_memory_address_remap_entries_reserved_cmc
- Type:
- number
Defines which entries in the remap table per cmc is reserved (for Arm) and cannot be used by SDK. value is a bitmap, each bit represent an entry of the table example: host_memory_address_remap_entries_cmc_<cmc_index>=0x12
- Forms:
host_memory_address_remap_entries_reserved_cmc_<port>,host_memory_address_remap_entries_reserved_cmc_<type>,host_memory_address_remap_entries_reserved_cmc
- i2c_hclk_skip
- Type:
- number
PCF8574 lpt2 and LTC4258 poe3 share the same I2C slave address. Set this to 1 to treat the device found at this slave address as POE.
- i2c_nvram_skip
- Type:
- number
24c64 EEPROM and XFP share the same I2C slave address. Set this to 1 to treat the device found at this slave address as XFP.
- i2c_timeout_usec
- Type:
- number
The maximum wait time for a I2C transaction to complete in interrupt-driven mode.
- indirect_access_timeout_usec
- Type:
- number
- iproc_shutdown
- Type:
- number
- irq_adaptive_poll_mode
- Type:
- number
Adaptive IRQ poll mode. In case lot of interrupts are happening, interrupt thread switches to interrupt poll mode and switch back to kernel mode to wait for interrupt only when no interrupt status is pending. This feature is specific to cmicx based devices. Adaptive IRQ poll mode is enabled by default. It can be disabled by setting the configuration property to be 0.
- knet_filter_persist
- Type:
- number
- Default:
0
Do not create default KNET Rx filter and preserve existing KNET filters during BCM API initialization and shutdown.
- knetsync_pci_cosq
- Type:
- number
Reserved cosq on the host used for KNETSync packet handling between FW and the KO
- mdio_external_master
- Type:
- number
- Default:
0
Allow external MDIO master access. Otherwise, the switch device is the MDIO master.
- mdio_output_delay
- Type:
- number
- Default:
- unset
Number of clock delay between the rising edge of MDC and the starting data of MDIO By default, it sets the same clock delay on all MDIO rings. For CMICX devices,it can be suffixed with “_#” to selectively set it per MDIO ring.
- Forms:
mdio_output_delay_<N>
- memcmd_intr_enable
- Type:
- number
- Default:
0
- memcmd_timeout_usec
- Type:
- number
- Default:
1000000
Command memory controls
- miim_intr_enable
- Type:
- number
- Default:
0
If miim_intr_enable variable is set to 1, the system will use interrupts for MII operations since they take a while (70 usec or so). If this variable is set to 0, polling will be used for all MII operations.
- SONiC:
set in 36 Trident 3 HWSKU files;
0,1- On Seastone2:
miim_intr_enable=0
- miim_timeout_usec
- Type:
- number
MIIM operation timeout in microseconds
- msi_x_intr_clear_auto_mode_enable
- Type:
- number
Enable Auto mode to clear internal interrupt masks for MSI/MSIX interrupts. This feature is specific to cmicx based devices.
- msi_x_intr_delay_usec
- Type:
- number
Minimum delay between two MSI/MSI-X interrupts in micro seconds. This feature is specific to cmicx based devices.
- multi_sbus_cmds_spacing
- Type:
- number
- Default:
- unset
- num_pipe
- Type:
- number
- pci_cmc
- Type:
- number
- Default:
0
CMC in CMICm used by the PCI Host
- pci_cmcs_num
- Type:
- number
Number of CMC used by the PCI Host
- pcie_flash_mem_params
- Type:
- number
Parameter of the QSPI flash memory used to hold the PCIe firmware If the value is not empty, should specify the parameters of the flash memory: <ID>,<sector size>,<page size> ID: The one byte manufacturer ID of the flash chip. The rest of the parameters will be applied only if the read ID is equal to this one. sector size in bytes: The smallest part of the chip that can be erased, should be a multiple of the page size. page size in bytes: smallest access unit.
- pcie_host_intf_timeout_purge_enable
- Type:
- number
Enable Purge operation as soon as PCIE timeout is detected.
- pcie_host_intf_timeout_usec
- Type:
- number
PCIE host interface timeout in microseconds timeout value is based on 250 Mhz clock 1 usc = 0x100, Default is 50 msec
- pcie_hot_swap_timeout_usec
- Type:
- number
PCIE hot swap timeout in microseconds for IDLE/READY condition
- pdma_continuous_mode_enable
- Type:
- number
Enable support for packet I/O continuous DMA mode
- pdma_descriptor_prefetch_enable
- Type:
- number
Enable support for packet DMA descriptor prefetch mode. This feature enables descriptors contiguous in memory to be prefetched and thus increase packet dma throughput. This feature is specific to cmicx based devices.
- SONiC:
set in 10 Trident 3 HWSKU files;
1
- pdma_dv_free_count
- Type:
- number
This soc property defines the number of free DMA Vectors the SOC DMA driver will cache to avoid calling alloc/free routines The value can vary between 32 to 512.
- pdma_dv_free_size
- Type:
- number
This soc property defines the number of DCBs(dma control blocks) in the DMA vector. the value can vary between 160 to 640. This value has to be greater than pdma_dv_free_count property User has to make sure that enough memory is available to allocate these DCBs.
- pdma_max_err_count
- Type:
- number
Maximum number of consecutive PKTDMA errors.
- pdma_timeout_usec
- Type:
- number
Packet DMA abort timeout
- pktdma_poll_mode_channel_bitmap
- Type:
- number
This soc property indicates a channel bitmap which uses packet dma poll mode. Bit n is for channel n. The bit value 1 means poll mode, 0 means interrupt mode. Default value is 0x0. Example: pktdma_poll_mode_channel_bitmap=0x02 means channel 1 uses poll mode.
- SONiC:
set in 8 Trident 3 HWSKU files;
1
- pktio_driver_type
- Type:
- number
- Default:
0
Select packet I/O driver by specifying driver type. Value: 0: classic (default type). Use bcm_tx/bcm_rx API set. 1: streamlined. Use bcm_pktio API set. Valid only for devices that support streamlined packet I/O driver.
- polled_irq_delay
- Type:
- number
The priority of the IRQ poll thread as well as the minimum delay between IRQ polls can be configured if needed.
- polled_irq_mode
- Type:
- number
- Default:
0
Enable polled IRQ mode (useful for board bringup and debugging). IRQs will be polled from a dedicated thread and hardware interrupts will remain disabled.
- polled_irq_priority
- Type:
- number
The priority of the IRQ poll thread as well as the minimum delay between IRQ polls can be configured if needed.
- rate_<bus>_<dividend|divisor>
- Type:
- number
Clock divider for the internal or external MDIO bus, the I2C bus or the stats DMA, as a dividend/divisor pair applied to the core clock. Board-specific; leave at the default unless the board vendor says otherwise.
- Names:
rate_ext_mdio_dividend,rate_ext_mdio_divisor,rate_i2c_dividend,rate_i2c_divisor,rate_int_mdio_dividend,rate_int_mdio_divisor,rate_stdma_dividend,rate_stdma_divisor
- reserved_rdbgc
- Type:
- number
Indicate reserved RDBGC counters. reserved_rdbgc_x controls RDBGCx. By default RDBGC1-2 are reserved. 0 – Unreserve the RDBGC counter. 1 – Reserve the RDBGC counter.
- rx_pool_nof_pkts
- Type:
- number
Specifies number of packets for BCM RX buffer allocation. This is equal to number of channels x chains per channel x descriptors per chain. For multi unit systems, the resulting value needs to be multiplied by number of units.
- sbus_dma_desc_thread_pri
- Type:
- number
Specifies the priority of the socdmadesc thread
- sbusdma_flush_cache_enable
- Type:
- number
Enable cache flush for SBUSDMA.
- schan_error_block_usec
- Type:
- number
- Default:
250000
Length of time to block the S-Channel error interrupt after one occurs. Prevents monopolizing the CPU (use 0 to disable any blocking).
- schan_intr_enable
- Type:
- number
- Default:
1
Normally, the system will use polling for register/memory S-Channel operations and interrupts for time-consuming operations such as ARL insert/delete. If this schan_intr_enable is set to 0, polling will be used for ALL operations.
- SONiC:
set in 33 Trident 3 HWSKU files;
0- On Seastone2:
schan_intr_enable=0
- schan_timeout_retry_enable
- Type:
- number
Retry S-Channel operations in timeout. By default, value 0 disables the retry.
- schan_timeout_usec
- Type:
- number
S-Channel operation timeout in microseconds. Note that ARL insert/delete messages can take a while if the ARL is highly active.
- schanfifo_intr_enable
- Type:
- number
- Default:
1
SCHAN FIFO operation should use interrupt rather than poll for completion
- schanfifo_timeout_usec
- Type:
- number
- Default:
30000000
SCHAN FIFO operation timeout in microseconds
- soc_counter_control_level
- Type:
- string
stat info will include the specific priotity and higher priorities possible values: LOW_LEVEL, MEDIUM_LEVEL, HIGH_LEVEL.
- soc_counter_max_dma_err_count
- Type:
- number
Maximum number of consecutive DMA errors during counter collection.
- soc_dma_monitor_thread_pri
- Type:
- number
Specifies the priority of the dma monitor thread thread(bcmDmaIntrM)
- soc_knet_rx_thread_pri
- Type:
- number
Specifies the priority of the SOC KNET RX thread
- stat_custom_receive0_management_mode
- Type:
- number
- Default:
0
- tdma_intr_enable
- Type:
- number
- Default:
1
Use an interrupt rather than polling to wait for table DMA.
- SONiC:
set in 8 Trident 3 HWSKU files;
1
- tdma_timeout_usec
- Type:
- number
Table DMA operation timeout in microseconds
- SONiC:
set in 42 Trident 3 HWSKU files;
3000000,5000000,15000000- On Seastone2:
tdma_timeout_usec=3000000
- tslam_dma_enable
- Type:
- number
- Default:
1
Enable/Disable SLAM DMA
- tslam_intr_enable
- Type:
- number
- Default:
1
Use an interrupt rather than polling to wait for table-write DMA (SLAM).
- tslam_timeout_usec
- Type:
- number
Table SLAM DMA operation timeout in microseconds
- SONiC:
set in 9 Trident 3 HWSKU files;
15000000