Ports, lanes and SerDes

Logical-to-physical port mapping, breakout, lane swaps and polarity, transmit equalisation, auto-negotiation and link scanning. See Port mapping and SerDes for the formats and worked examples.

Set in several SONiC Trident 3 HWSKU files: dport_map_enable, dport_map_port, higig2_hdr_mode, module_64ports, oversubscribe_mixed_sister_25_50_enable, oversubscribe_mode, pbmp_gport_stack, pbmp_oversubscribe, pbmp_xport_xe, phy_an_c37, phy_an_c73, phy_chain_rx_lane_map_physical, phy_chain_rx_polarity_flip_physical, phy_chain_tx_lane_map_physical, phy_chain_tx_polarity_flip_physical, phy_port_primary_and_offset, port_flex_enable, port_gmii_mode, port_init_autoneg, port_phy_addr, portmap, serdes_core_rx_polarity_flip_physical, serdes_core_tx_polarity_flip_physical, serdes_driver_current, serdes_if_type, serdes_preemphasis.

bcm_boot_abort_on_mac_init_fail
Type:
number
bcm_linkscan_errdelay
Type:
number
Default:
10000000

The amount of time in microseconds for which the bcm_linkscan module will suspend a port from further update processing after “bcm_linkscan_maxerr” errors are detected. After this delay, the error state for the port is cleared and normal linkscan processing resumes on the port.

Forms:

bcm_linkscan_errdelay_<port>, bcm_linkscan_errdelay_<type>, bcm_linkscan_errdelay

bcm_linkscan_interval
Type:
number
Default:
250000

Link scan interval in microseconds. The SAI starts link scanning with this interval.

Forms:

bcm_linkscan_interval_<port>, bcm_linkscan_interval_<type>, bcm_linkscan_interval

bcm_linkscan_maxerr
Type:
number
Default:
5

The number of port update errors which will cause the bcm_linkscan module to suspend a port from update processing for the period of time set in “bcm_linkscan_errdelay”.

Forms:

bcm_linkscan_maxerr_<port>, bcm_linkscan_maxerr_<type>, bcm_linkscan_maxerr

bcm_linkscan_pbmp
Type:
number

Linkscan: Specify ports on which bcm_init will run linkscan (default all).

bcm_xlate_api_port_enable
Type:
number

Enable translation of physical port numbers within the BCM layer. This feature allows a new device to emulate an older similar device even if the physical port map is different. Note that translation support must be compiled in as well.

bcm_xlate_port
Type:
number

Indication if the port should be remapped given a mapping function

bcm_xlate_port_enable
Type:
number

Convenience variable that can be used to turn off both physical and system port mapping. This variable overrides the dedicated variables described above.

bcm_xlate_port_map
Type:
string

String identification of port mapping function to be used.

bcm_xlate_sysport_enable
Type:
number

Enable translation of system port numbers to physical port numbers in hardware (if supported by the switch device). This feature may be used to complement the BCM API translation feature, but can also be used to limit the use of module IDs on devices with 32 or fewer ports in case some physical port numbers reside beyond 31.

dport_map_direct
Type:
number

Traditionally, specifying a raw number instead of a port name in the diag shell will be parsed as if port numbers are counted from 1 up to the number of enabled ports. Typically this would mean that for a gigabit switch, port 1 would correspond to ge0, and so forth. Setting this flag causes raw port numbers to be parsed as internal port numbers.

dport_map_enable
Type:
number

Enable the diag-shell port numbering set with dport_map_port. Has no effect on forwarding or on SONiC.

SONiC:

set in 13 Trident 3 HWSKU files; 1, 0

dport_map_indexed
Type:
number

Port names for each port type (fe, ge, etc.) will increment by one starting at zero, e.g. if a switch has four xe ports with dport numbers 24, 25, 26, and 27, they will be named xe0, xe1, xe2, and xe3. In non-indexed mode the ports would be named xe24, xe25, xe26, and xe27.

dport_map_port
Type:
number
Default:
unset

Diag-shell port number for logical port <port>: dport_map_port_<port>=<dport>. Only changes how bare numbers are read in shell commands (see Port bitmap grammar); needs dport_map_enable.

Forms:

dport_map_port_<logical port>

SONiC:

set in 35 Trident 3 HWSKU files; 6, 2, 1

eee_phy_config_ignore
Type:
number
Default:
0

PHY config ingnored for EEE controls

ext_phy_autodetect_en
Type:
number

To enable/disable the SGMII Slave Autodetect function 0x0 = Disable SGMII Slave Auto-detect function 0x1 = Enable SGMII Slave Auto-detect function

Forms:

ext_phy_autodetect_en_<port>, ext_phy_autodetect_en_<type>, ext_phy_autodetect_en

ext_phy_serdes_fiber_iface
Type:
number

Select Fiber Interface when SGMII Slave Autodetect is disabled 0x0 = 1000Base-X, 0x1 = 100Base-FX, 0x2 = SGMII-Slave.

Forms:

ext_phy_serdes_fiber_iface_<port>, ext_phy_serdes_fiber_iface_<type>, ext_phy_serdes_fiber_iface

fabric_port_enable
Type:
number
Default:
1

BCM5696X : 0 => Disable support for Ethernet to HiGig2 transformation 1 => Enable support for Ethernet to HiGig2 transformation Ethernet to HiGig2 transformation involves two steps - Encapsulation change from IEEE to HiGig2 and - Port speed change from Ethernet port speeds to HiGig2 port speeds When fabric_port_enable=0, encapsulation changes are still permitted, but Ethernet to HiGig2 speed change is disallowed. If the initial portmap contains HiGig2 ports then fabric_port_enable config is ignored

fast_sw_rx_los_pbmp
Type:
number
Default:
0
fcmap_enable
Type:
number
Default:
0

Specifies to enable or disable FCMAP feature on the specified port. FCMAP feature might be provided by a PHY device attached to switch port. (Default is to disable FCMAP)

Forms:

fcmap_enable_<port>, fcmap_enable_<type>, fcmap_enable

flex_port_phy_addr
Type:
number

Configure the PHY address(es) for the flex-ports

Forms:

flex_port_phy_addr_<port>, flex_port_phy_addr_<type>, flex_port_phy_addr

higig2_hdr_mode
Type:
number

Make all HG ports default to HiGig2.

Forms:

higig2_hdr_mode_<port>, higig2_hdr_mode_<type>, higig2_hdr_mode

SONiC:

set in 9 Trident 3 HWSKU files; 1

higig2_multicast_l2_range
Type:
number

Multicast ranges This value sets the allowed range of multicast indices in the Higig2 header for stack ports.

higig2_multicast_l3_range
Type:
number

Multicast ranges This value sets the allowed range of IP multicast indices in the Higig2 header for stack ports.

higig2_multicast_vlan_range
Type:
number

Multicast ranges The Higig2 header format concatenates the broadcast, multicast, and IP multicast indices into one generic multicast index. The mapping between the individual indices and the combined index is specified by these. The default values are indicated. This value sets the allowed range of broadcast indices in the Higig2 header for stack ports.

link_delay_<speed>_ns
Type:
number

Link delay in nanoseconds reported for ports of one speed, used for timestamp correction; link_delay_ns for all other speeds.

Names:

link_delay_100gbe_ns, link_delay_100mbe_ns, link_delay_10gbe_ns, link_delay_10mbe_ns, link_delay_1gbe_ns, link_delay_200gbe_ns, link_delay_20gbe_ns, link_delay_25gbe_ns, link_delay_2_5gbe_ns, link_delay_400gbe_ns, link_delay_40gbe_ns, link_delay_50gbe_ns, link_delay_ns

linkscan_thread_pri
Type:
number
Default:
50

Specifies the priority of the BCM Linkscan thread

mac_length_check_enable
Type:
number
Default:
0

Enable MAC to check 802.3 frame length field

mac_line_lb
Type:
number
Forms:

mac_line_lb_<port>, mac_line_lb_<type>, mac_line_lb

max_mtu_size
Type:
number

This soc property is used to specify max mtu size for the device. If this is not specified, the defalut mtu size supported by the device is used as max mtu

mld_lane_swap
Type:
number

Swap MLD lane tx lane 0 through 23

module_64ports
Type:
number

Use 64 ports per module identifier. Set in many SONiC Trident 3 files, but not read by the SDK on a running SONiC Trident 3 switch.

SONiC:

set in 42 Trident 3 HWSKU files; 1, 0

On Seastone2:

module_64ports=1; not read by the SDK on that switch

oversubscribe_mixed_sister_25_50_enable
Type:
number
Default:
0

Allow 25G and 50G ports on sister lanes of the same core in mixed oversubscription mode. Set by some SONiC Trident 3 files together with pbmp_oversubscribe.

SONiC:

set in 10 Trident 3 HWSKU files; 1

oversubscribe_mode
Type:
port bitmap
Default:
0

0 line rate, 1 all ports oversubscribed, 2 mixed (ports in pbmp_oversubscribe). On Trident 3 a 100G port is only accepted in oversubscribed mode, so every 32×100G SONiC file sets 1.

SONiC:

set in 45 Trident 3 HWSKU files; 1, 2

On Seastone2:

oversubscribe_mode=1

pbmp_gport_stack
Type:
port bitmap
Default:
0

Port bitmap of HiGig stacking ports. SONiC Trident 3 files set it to all zeros (pbmp_gport_stack.0=0x0…).

SONiC:

set in 7 Trident 3 HWSKU files; 0x0000000000000000000000000000000000000000000000000000000000000000

On Seastone2:

pbmp_gport_stack.0=0x0000000000000000000000000000000000000000000000000000000000000000

pbmp_oversubscribe
Type:
port bitmap
Default:
0

Port bitmap of the ports to run oversubscribed when oversubscribe_mode is 2 (mixed).

SONiC:

set in 12 Trident 3 HWSKU files; 0x6fffffffffffffffdfffffffffffffffe, 0x7fff9fffffffffffffffe, 0x7f878787f878787f9fe1e1e1fe1e1e1fe

pbmp_oversubscribe_mixed_sister_25_50_init
Type:
port bitmap

Port bitmap for 25G ports use 50G TDM calendar during initialization. It refers to logical port number. This SOC property only apply to TH2 and other devices which use new type flex port API(bcm_port_resource_multi_set).

pbmp_subport
Type:
port bitmap
Default:
0

Port bitmap for ports that support subport feature. This specifies subport feature to be enabled with any mode of vlan tag based or LinkPHY channel/stream based.

pbmp_xport_ge
Type:
port bitmap

Some BCM56xxx devices, such as the BCM568xx series, allow the XPORTs to be configured as XE, HG, and GE ports. XPORTs set in this bitmap will be GE ports.

SONiC:

set in 1 Trident 3 HWSKU file; 0x00001fffffffffffe

pbmp_xport_xe
Type:
port bitmap

Port bitmap (logical ports, hexadecimal) of the ports that come up as Ethernet ports. Every SONiC Trident 3 file sets all front-panel ports.

SONiC:

set in 47 Trident 3 HWSKU files; 0x3ffffffffffffffffffffffffffffffffe, 0x6fffffffffffffffdfffffffffffffffe, 0xffffffffffffffffffffffffffffffffffffffffe

On Seastone2:

pbmp_xport_xe=0x3ffffffffffffffffffffffffffffffffe

phy_an_allow_pll_change
Type:
number

This controls if pll change allowed during AN enable(1), disable(0).

Forms:

phy_an_allow_pll_change_<port>, phy_an_allow_pll_change_<type>, phy_an_allow_pll_change

phy_an_c37
Type:
number
Default:
0

Clause 37 auto-negotiation of a port (1G): 0 off, 1 CL37 with BAM, 2 CL37 without BAM.

Forms:

phy_an_c37_<port>, phy_an_c37_<type>, phy_an_c37

SONiC:

set in 4 Trident 3 HWSKU files; 2

phy_an_c72
Type:
number
Default:
1

Clause 72 link training on a port: 1 on, 0 off.

Forms:

phy_an_c72_<port>, phy_an_c72_<type>, phy_an_c72

phy_an_c72_tx_init_skip_on_restart
Type:
number
Default:
0

skip the TXFIR initialization in a restart event during the AN link training, and initialize TXFIR in 1G mode (CL73 AN) to (0,100,0). This configure is for 25G with short cable in Falcon/Falcon16 core. enable(1), disable(0).

Forms:

phy_an_c72_tx_init_skip_on_restart_<port>, phy_an_c72_tx_init_skip_on_restart_<type>, phy_an_c72_tx_init_skip_on_restart

phy_an_c73
Type:
number
Default:
0

Clause 73 auto-negotiation mode of a port: 0 off, 1 CL73 with BAM, 2 CL73 without BAM, 3 CL73 and MSA, 4 MSA only, 5 CL73 and CL37. phy_an_c73=1 sets all ports; phy_an_c73_<port>=0 excludes one.

Forms:

phy_an_c73_<port>, phy_an_c73_<type>, phy_an_c73

SONiC:

set in 27 Trident 3 HWSKU files; 1, 0, 3

On Seastone2:

phy_an_c73=1

phy_an_fec
Type:
number

This controls the clause 91(FEC) enable(2), the clause 74(FEC) enable(1), disable(0).

Forms:

phy_an_fec_<port>, phy_an_fec_<type>, phy_an_fec

phy_an_lt_msft
Type:
number

Enable the Microsoft link-training variant on a port. Set by some SONiC Trident 3 files.

SONiC:

set in 2 Trident 3 HWSKU files; 1

phy_autoneg_master_lane
Type:
number
Default:
0

This SOC property is used to select the auto-negotiation master lane for a port. The auto-negotiation master lane selection should be done by the user prior to enabling auto-negotiation.

Forms:

phy_autoneg_master_lane_<port>, phy_autoneg_master_lane_<type>, phy_autoneg_master_lane

phy_autoneg_timeout
Type:
number

Per-port parameter on maximum time to wait for PHY autoneg busy condition.

Forms:

phy_autoneg_timeout_<port>, phy_autoneg_timeout_<type>, phy_autoneg_timeout

phy_chain_length
Type:
number
Default:
0

This specifies the position of external phy in the phy chain.

Forms:

phy_chain_length_<port>, phy_chain_length_<type>, phy_chain_length

phy_chain_rx_lane_map_physical
Type:
number
Default:
0x3210

Receive lane swap of the internal SerDes core whose first lane is physical port N, in the same format as phy_chain_tx_lane_map_physical.

Forms:

phy_chain_rx_lane_map_physical{<physical>.<phy>}, phy_chain_rx_lane_map_physical{<physical>}, phy_chain_rx_lane_map_physical_<port>, phy_chain_rx_lane_map_physical

SONiC:

set in 46 Trident 3 HWSKU files; 0x3210, 0x1032, 0x2031

On Seastone2:

phy_chain_rx_lane_map_physical{89.0}=0x2031, phy_chain_rx_lane_map_physical{113.0}=0x2031, phy_chain_rx_lane_map_physical{21.0}=0x2031, phy_chain_rx_lane_map_physical{29.0}=0x2031 and 29 more

phy_chain_rx_polarity_flip_physical
Type:
number
Default:
0x0

Invert the receive P/N polarity of physical lane N, as phy_chain_tx_polarity_flip_physical.

Forms:

phy_chain_rx_polarity_flip_physical{<physical>.<phy>}, phy_chain_rx_polarity_flip_physical{<physical>}, phy_chain_rx_polarity_flip_physical_<port>, phy_chain_rx_polarity_flip_physical

SONiC:

set in 45 Trident 3 HWSKU files; 0x0, 0x1, 0xf

On Seastone2:

phy_chain_rx_polarity_flip_physical{16.0}=0x1, phy_chain_rx_polarity_flip_physical{94.0}=0x1, phy_chain_rx_polarity_flip_physical{59.0}=0x0, phy_chain_rx_polarity_flip_physical{1.0}=0x0 and 128 more

phy_chain_tx_lane_map_physical
Type:
number
Default:
0x3210

Transmit lane swap of the internal SerDes core whose first lane is physical port N: phy_chain_tx_lane_map_physical{N.0}=0x<l3><l2><l1><l0>. One hexadecimal digit per lane, lane 0 in the lowest digit. .0 selects the internal SerDes; .1 and up are external PHYs. Board wiring; copy it from the vendor’s file.

Forms:

phy_chain_tx_lane_map_physical{<physical>.<phy>}, phy_chain_tx_lane_map_physical{<physical>}, phy_chain_tx_lane_map_physical_<port>, phy_chain_tx_lane_map_physical

SONiC:

set in 46 Trident 3 HWSKU files; 0x3210, 0x0123, 0x2301

On Seastone2:

phy_chain_tx_lane_map_physical{49.0}=0x2103, phy_chain_tx_lane_map_physical{93.0}=0x0312, phy_chain_tx_lane_map_physical{33.0}=0x0213, phy_chain_tx_lane_map_physical{125.0}=0x0123 and 29 more

phy_chain_tx_polarity_flip_physical
Type:
number
Default:
0x0

Invert the transmit P/N polarity of physical lane N: phy_chain_tx_polarity_flip_physical{N.0}=1. One variable per lane. Board wiring; copy it from the vendor’s file.

Forms:

phy_chain_tx_polarity_flip_physical{<physical>.<phy>}, phy_chain_tx_polarity_flip_physical{<physical>}, phy_chain_tx_polarity_flip_physical_<port>, phy_chain_tx_polarity_flip_physical

SONiC:

set in 45 Trident 3 HWSKU files; 0x0, 0x1

On Seastone2:

phy_chain_tx_polarity_flip_physical{34.0}=0x0, phy_chain_tx_polarity_flip_physical{77.0}=0x0, phy_chain_tx_polarity_flip_physical{2.0}=0x0, phy_chain_tx_polarity_flip_physical{117.0}=0x1 and 128 more

phy_driver_current
Type:
number

Configure the given driver current value for applicable external phy devices.

Forms:

phy_driver_current_lane<N>_<port>, phy_driver_current_<port>, phy_driver_current

phy_enable
Type:
number

If phy_enable is set to 0, all ports will use the null PHY driver. This is useful for simulations on Quickturn.

phy_force_firmware_load
Type:
number

Firmware load policy for PHYs: 0 may skip the load, 1 force, 2 automatic; with 1, the second hexadecimal digit selects the download method (0x11 force over MDIO). The SAI sets it itself on some boot paths.

Forms:

phy_force_firmware_load_<port>, phy_force_firmware_load_<type>, phy_force_firmware_load

phy_gearbox_enable
Type:
number
Default:
0

Mark a port as connected through an external gearbox PHY.

Forms:

phy_gearbox_enable_<port>, phy_gearbox_enable_<type>, phy_gearbox_enable

phy_init_flr_enable
Type:
string

This property specifies the flr support and flr enable for the certain port. Format: phy_init_flr_enable_lport=flr_support:timeout_time lport: logic port id. flr_support : choose if to download the flr ucode. timeout_time: timeout time, the format of timeout_time is 0 ————-FLR disable 1 ————-FLR enable with timeout_time=50ms 2 ————-FLR enable with timeout_time=75ms 3 ————-FLR enable with timeout_time=100ms 4 ————-FLR enable with timeout_time=150ms 5 ————-FLR enable with timeout_time=250ms 6 ————-FLR enable with timeout_time=500ms For Example: phy_init_flr_enable_1=1:0 Download flr ucode on the PM core that port 1 is attached, but not enable flr on port 1. phy_init_flr_enable_1=1:1 Download flr ucode on the PM core that port 1 is attached, and enable flr on port 1 with timeout of 50ms.

Forms:

phy_init_flr_enable_<port>, phy_init_flr_enable_<type>, phy_init_flr_enable

phy_init_speed
Type:
number

Default speed that the external PHY will initialize with

Forms:

phy_init_speed_<port>, phy_init_speed_<type>, phy_init_speed

phy_mod_auto_detect
Type:
number

Enable module auto detection for devices that are able to detect when a module is inserted or removed. 0 disable, 1 enable

Forms:

phy_mod_auto_detect_<port>, phy_mod_auto_detect_<type>, phy_mod_auto_detect

phy_pcs_repeater
Type:
number
Default:
0

Bypass the PCS retimer function to provide better latency. However it requires a more clean input clock than in retimer mode

Forms:

phy_pcs_repeater_<port>, phy_pcs_repeater_<type>, phy_pcs_repeater

phy_pcs_rx_polarity_flip
Type:
number

Flip PCS lane RX polarity. See phy_xaui_tx_polarity_flip for values

Forms:

phy_pcs_rx_polarity_flip_<port>, phy_pcs_rx_polarity_flip_<type>, phy_pcs_rx_polarity_flip

phy_pcs_tx_polarity_flip
Type:
number

Flip PCS lane TX polarity. See phy_xaui_tx_polarity_flip for values

Forms:

phy_pcs_tx_polarity_flip_<port>, phy_pcs_tx_polarity_flip_<type>, phy_pcs_tx_polarity_flip

phy_port_primary_and_offset
Type:
number

Base port and slice of a multi-port external PHY: phy_port_primary_and_offset_<port>=0xPPOO (primary port, slice offset). Only for boards with an external PHY.

Forms:

phy_port_primary_and_offset_<port>, phy_port_primary_and_offset_<type>, phy_port_primary_and_offset

SONiC:

set in 4 Trident 3 HWSKU files; 0x0100, 0x0101, 0x0102

phy_preemphasis
Type:
number

Configure the given preemphasis value for applicable external phy devices.

Forms:

phy_preemphasis_lane<N>_<port>, phy_preemphasis_<port>, phy_preemphasis

phy_reset_timeout
Type:
number

Specify IEEE MII reset timeout value for copper PHY devices

phy_rx_lane_map
Type:
number

Legacy receive lane map of a port; on Trident 3 use phy_chain_rx_lane_map_physical.

Forms:

phy_rx_lane_map{<physical>.<phy>}, phy_rx_lane_map{<physical>}, phy_rx_lane_map_<port>, phy_rx_lane_map

phy_rx_los
Type:
number

Enable Loss Of Signal(LOS) function. 0 disable, 1 enable

Forms:

phy_rx_los_<port>, phy_rx_los_<type>, phy_rx_los

phy_rx_los_invert
Type:
number

Invert PHYs LOS signal level. 0 not invert, 1 invert

Forms:

phy_rx_los_invert_<port>, phy_rx_los_invert_<type>, phy_rx_los_invert

phy_rx_polarity_flip
Type:
number

Legacy per-port receive polarity flip (bit per lane); on Trident 3 SONiC files use phy_chain_rx_polarity_flip_physical.

Forms:

phy_rx_polarity_flip{<physical>.<phy>}, phy_rx_polarity_flip{<physical>}, phy_rx_polarity_flip_<port>, phy_rx_polarity_flip

phy_sys_interface
Type:
number

Specify the sytem side interface to be configured for the PHY

Forms:

phy_sys_interface_<port>, phy_sys_interface_<type>, phy_sys_interface

phy_topology
Type:
number

This specifies the position of external phy in the phy chain. For Recent PHY devices, logical ports can span across multiple cores These cores could be connected to multi-core external PHYs or Single core multi-lane external PHYs This presents complex topology options. Here is the format of the new config variable: Format1: phy_topology_pport_xphyId=mdio-addr:sys_lane:line_lane Format2: phy_topology_pport_xphyId_mapX=mdio-addr:sys_lane:line_lane where: pport = physical port number xphyId = position of the external PHY in the chain mdio_addr = mdio address of the external phy sys_lane = system side physical lane number line_lane = line side physical lane number mapX = index of lane mapping for specific pport and xphyId The above mentioned config would help in figuring out the physical lane numbers associated with the logical port to enable programming where there is no logical to logical lane mapping Here is an example for format1 case that show multiple cores connected to a external phy and it corresponding topology config ________ ________ | |________| | | | | | | |________| | | CORE0 | | EXTPHY | | |________| | | | | | | |________| | |________| | | | | Sys side | | ________ | | | | | | Line side | |\ | |__________ | | \ | | | CORE0 |\ \ /| |__________ | | \ \ / | | | |\ \ \/ /| |__________ | | \ \/\/ | | |________|\ \/\/\/| |__________ \/\/\/\| | ________ /\/\/\ | | | |/ /\/\ \| | | | / /\ \ | | | |/ / \ \| | | CORE0 | / \ | EXTPHY | | |/ \| | | | | | | |________| | |________| |________| In the above image the physical lane swap crossed the core boundary on core1&2 and there is no logical to logical mapping for lanes 4 to 11 on the system side of ExtPhy with the internal PHY. If the user wants to run the PRBS on logical lane 4 (on internal PHY core1 logical lane 0), the driver can query the DB and get the necessary physical lane information (physical lane 8 in this case). Here is an example for format2 case that show the mux mode that one core connects to a external phy and it corresponding topology config ________ | | ________ | |__________ | |________| |__________\ | | | |__________ - PORT1 | |________| |__________/ | | | | | CORE | | EXTPHY | | |________| |__________ | | | |__________\ | |________| |__________ - PORT2 |________| | |__________/ | | |________| Sys side Line side In the above image, port1 and port2 map 4 line lanes and 2 system lines. There is no logical to logical mapping for lanes 0 to 7 on the system side of ExtPhy with the internal PHY. Here is an example to describe the relation. The format just describes the lane bitmap related with the port. Port1: mdio-addr is supposed to 0x10 and the first physical port is supposed to 0x8 phy_topology_8_1_map1=0x10:0:0 phy_topology_8_1_map2=0x10:0:1 phy_topology_9_1_map1=0x10:1:2 phy_topology_9_1_map2=0x10:1:3 Port2: phy_topology_10_1_map1=0x10:1:4 phy_topology_10_1_map2=0x10:1:5 phy_topology_11_1_map1=0x10:1:6 phy_topology_11_1_map2=0x10:1:7

Forms:

phy_topology_<N>

phy_tx_lane_map
Type:
number

Legacy transmit lane map of a port; on Trident 3 use phy_chain_tx_lane_map_physical.

Forms:

phy_tx_lane_map{<physical>.<phy>}, phy_tx_lane_map{<physical>}, phy_tx_lane_map_<port>, phy_tx_lane_map

phy_tx_polarity_flip
Type:
number

Legacy per-port transmit polarity flip (bit per lane); on Trident 3 SONiC files use phy_chain_tx_polarity_flip_physical.

Forms:

phy_tx_polarity_flip{<physical>.<phy>}, phy_tx_polarity_flip{<physical>}, phy_tx_polarity_flip_<port>, phy_tx_polarity_flip

phy_ull_datapath
Type:
number

Specify the data path mode to be configured for the PHY

Forms:

phy_ull_datapath_<port>, phy_ull_datapath_<type>, phy_ull_datapath

port_allow_tpid_disable
Type:
number

Allows default TPID on ports to be disabled. When all TPID are deleted from a port, the default TPID is added back. If enabled, this control will prevent a port from automatically adding the default TPID back to that port. port_allow_tpid_disable{logical port number}=0 or 1 Valid values are 0 or 1. Default value is 0.

Forms:

port_allow_tpid_disable_<port>, port_allow_tpid_disable_<type>, port_allow_tpid_disable

port_fc_type
Type:
number
Forms:

port_fc_type{<physical>.<phy>}, port_fc_type{<physical>}, port_fc_type_<port>, port_fc_type

port_fec
Type:
number
Default:
unset

FEC mode of a port at start-up: 0 none, 1 CL74 (Base-R), 2 CL91 (RS-FEC). SONiC sets FEC through the SAI instead.

Forms:

port_fec_<port>, port_fec_<type>, port_fec

port_flex_enable
Type:
number
Default:
0

Allow the four-lane core that holds physical port N to be reconfigured at runtime (breakout, speed and lane changes through SONiC dynamic port breakout or port). port_flex_enable=1 enables all cores; port_flex_enable{<physical>}=0 or port_flex_enable_<logical>=0 excludes one, as SONiC files do for the management ports. Set it on the first lane of a core.

Forms:

port_flex_enable{<physical>.<phy>}, port_flex_enable{<physical>}, port_flex_enable_<port>, port_flex_enable

SONiC:

set in 44 Trident 3 HWSKU files; 1, 0

On Seastone2:

port_flex_enable=1

port_flex_max_ports
Type:
number

Maximum number of ports a core can be split into: 1, 2 or 4 (default 4), set on the first physical port of the core, port_flex_max_ports{<physical>}.

Forms:

port_flex_max_ports{<physical>.<phy>}, port_flex_max_ports{<physical>}, port_flex_max_ports_<port>, port_flex_max_ports

port_gmii_mode
Type:
number
Default:
0

Mode of a port macro on chips with QSGMII-capable cores: 0 Ethernet, 1 QSGMII, 2 USGMII; set on the first physical port of the macro.

Forms:

port_gmii_mode{<physical>.<phy>}, port_gmii_mode{<physical>}, port_gmii_mode_<port>, port_gmii_mode

SONiC:

set in 4 Trident 3 HWSKU files; 1

port_init_adv
Type:
number
Default:
unset

Default local advertisement settings for a port

Forms:

port_init_adv_<port>, port_init_adv_<type>, port_init_adv

port_init_autoneg
Type:
number
Default:
unset

Enable auto-negotiation on a port at start-up (port_init_autoneg_<port>=1). SONiC usually overrides it through the SAI.

Forms:

port_init_autoneg_<port>, port_init_autoneg_<type>, port_init_autoneg

SONiC:

set in 7 Trident 3 HWSKU files; 0, 1

port_init_cl72
Type:
number

Initialize port with CL72 enabled

Forms:

port_init_cl72_<port>, port_init_cl72_<type>, port_init_cl72

port_init_duplex
Type:
number
Default:
unset

Default duplex mode the port will initialize with

Forms:

port_init_duplex_<port>, port_init_duplex_<type>, port_init_duplex

port_init_speed
Type:
number

Speed of a port at start-up in Mb/s. SONiC sets speeds from port_config.ini through the SAI.

Forms:

port_init_speed_<port>, port_init_speed_<type>, port_init_speed

port_max_speed
Type:
number

overwrite the default port max speed

Forms:

port_max_speed_<port>, port_max_speed_<type>, port_max_speed

port_phy_addr
Type:
number
Default:
0

MDIO address of the external PHY of a port. Only for boards with an external PHY or gearbox.

Forms:

port_phy_addr_<port>, port_phy_addr_<type>, port_phy_addr

SONiC:

set in 10 Trident 3 HWSKU files; 0xff, 0x21, 0x22

port_phy_clause
Type:
number

MDIO Bus Property to select the MDIO access mechanism (CLAUSE22 / CLAUSE45)

Forms:

port_phy_clause_<port>, port_phy_clause_<type>, port_phy_clause

port_phy_id0
Type:
number

First part of a uniqe PHY identifier, if not specified in register

port_phy_id1
Type:
number

Second part of a uniqe PHY identifier, if not specified in register

port_phy_mode_reverse
Type:
number

Phy operating in the reverse direction. To set reverse mode for phy84728 and phy8706 set port_phy_mode_reverse_phy84728 and set port_phy_mode_reverse_phy8706

Forms:

port_phy_mode_reverse_<port>, port_phy_mode_reverse_<type>, port_phy_mode_reverse

port_phy_precondition_before_probe
Type:
number

This controls whether to precondition this port before probing of PHY on this port for applicable PHY devices, precondition(1)/not(0).

Forms:

port_phy_precondition_before_probe_<port>, port_phy_precondition_before_probe_<type>, port_phy_precondition_before_probe

port_priorities
Type:
number
Default:
0

Set the number of Outgoing local port queue-pairs (1/2/8) per port

port_sched_hsp
Type:
number

use HSP scheduler for the port. On TD2/TD2+ chip, only the lowest 16 MMU port numbers on each pipe can be configured to reside in the HSP scheduler. Port that enabled in the HSP scheduler, reserves an additional MMU port with offset of 36.

Forms:

port_sched_hsp_<port>, port_sched_hsp_<type>, port_sched_hsp

portmap
Type:
string

Creates logical port <port> on physical lane <physical> with a maximum speed in Gb/s: portmap_<port>=<physical>:<speed>[:<option>][:<option>]. Options are a lane count (1, 2, 4), i (inactive: created but disabled, a placeholder for later breakout) or m (management port), or a speed cap for flex ports. Valid speeds are 1, 2.5, 10, 11, 20, 21, 25, 27, 40, 42, 50, 53, 100 and 106; 100 and 106 need oversubscribe_mode. Physical lanes 1–128 are the front-panel SerDes, 129 (and 128 with m) the management port. See Port mapping and SerDes.

Forms:

portmap_<logical port>

SONiC:

set in 47 Trident 3 HWSKU files; 121:100, 125:100, 41:100

On Seastone2:

portmap_9=9:10:1, portmap_10=10:10:1, portmap_123=121:100, portmap_115=113:100 and 32 more

portmon_interval
Type:
number

Interval (in usecs) at which the port monitor thread will run. The port monitor can be used to handle workarounds which are required only with specific equipment configurations.

portmon_thread_pri
Type:
number
Default:
50

Specifies the priority of the BCM Portmon thread

rcpu_port
Type:
number
Default:
unset

switch port connected to slave RCPU device.

rsvd4_port_init_speed_id
Type:
number
Default:
unset

Initial speed for rsvd4 port Speeds 4: 3072.0 8: 6144.0

Forms:

rsvd4_port_init_speed_id_<port>, rsvd4_port_init_speed_id_<type>, rsvd4_port_init_speed_id

Type:
number
Default:
unset

Enables accelerated linkscan mode on specified port.

Forms:

rx_fast_los_link_<port>, rx_fast_los_link_<type>, rx_fast_los_link

rx_fast_los_poll_count_max
Type:
number

Indicates the maximum number of times linkscan will poll in accelerated mode without a status change in any accelerated mode ports.

rx_fast_los_usec
Type:
number

Indicates the linkscan time interval in usecs during accelerated mode.

same_speed_intf_do_not_overwrite
Type:
number

This soc property is used to enable whether overwrite the speed when the new speed/interface is same as current 0 => Overwrite the speed no matter the new spseed and interface 1 => Do not overwrite the speed if the new speed/interface is same as current

serdes_asymmetric_speed_mode
Type:
number

Enable Asymmetric fixed speed mode. 1 enable

Forms:

serdes_asymmetric_speed_mode_<port>, serdes_asymmetric_speed_mode_<type>, serdes_asymmetric_speed_mode

serdes_core_rx_polarity_flip_physical
Type:
number

Per-core polarity variable of newer chips. Found in some SONiC Trident 3 files, but this build reads it only for other chips; use phy_chain_rx_polarity_flip_physical.

Forms:

serdes_core_rx_polarity_flip_physical{<physical>.<phy>}, serdes_core_rx_polarity_flip_physical{<physical>}, serdes_core_rx_polarity_flip_physical_<port>, serdes_core_rx_polarity_flip_physical

SONiC:

set in 8 Trident 3 HWSKU files; 0xc, 0x3, 0x0

serdes_core_tx_polarity_flip_physical
Type:
number

Per-core polarity variable of newer chips. Found in some SONiC Trident 3 files, but this build reads it only for other chips; use phy_chain_tx_polarity_flip_physical.

Forms:

serdes_core_tx_polarity_flip_physical{<physical>.<phy>}, serdes_core_tx_polarity_flip_physical{<physical>}, serdes_core_tx_polarity_flip_physical_<port>, serdes_core_tx_polarity_flip_physical

SONiC:

set in 8 Trident 3 HWSKU files; 0x0, 0xc, 0x3

serdes_driver_current
Type:
number

Transmit driver current of a port’s SerDes lanes.

Forms:

serdes_driver_current_lane<N>_<port>, serdes_driver_current_<port>, serdes_driver_current

SONiC:

set in 5 Trident 3 HWSKU files; 0xf, 0xe

serdes_fec_enable
Type:
number

Enable forward error correction on a port’s SerDes at start-up. SONiC sets FEC per port through the SAI (fec in CONFIG_DB) instead.

Forms:

serdes_fec_enable_<port>, serdes_fec_enable_<type>, serdes_fec_enable

serdes_fifo_low_latency
Type:
number
Forms:

serdes_fifo_low_latency_<port>, serdes_fifo_low_latency_<type>, serdes_fifo_low_latency

serdes_firmware_mode
Type:
number

Serdes micro controller firmware mode

Forms:

serdes_firmware_mode_<port>, serdes_firmware_mode_<type>, serdes_firmware_mode

serdes_if_type
Type:
number

Interface type of a port as a number from the SDK’s interface list (9 SFI, 10 XFI, 11 KR, 12 KR4, 13 CR, 14 CR4, 15 XLAUI, 16 SR). serdes_if_type_ce=14 applies to every ce port. SONiC normally sets the interface type through the SAI instead.

Forms:

serdes_if_type_<port>, serdes_if_type_<type>, serdes_if_type

SONiC:

set in 7 Trident 3 HWSKU files; 14, 13, 16

On Seastone2:

serdes_if_type_ce=14

serdes_lane_config
Type:
string

SerDes lane options of a port, one variable per option: serdes_lane_config_dfe_<port>=on|off|lp, serdes_lane_config_media_type_<port>=backplane|copper|optics, serdes_lane_config_unreliable_los_<port>, serdes_lane_config_cl72_auto_polarity_en_<port>, serdes_lane_config_cl72_restart_timeout_en_<port>. The global serdes_lane_config_dfe=on found in some SONiC Trident 3 files was not read by the SDK on a running switch.

Forms:

serdes_lane_config_channel_mode<N>_<port>, serdes_lane_config_<port>, serdes_lane_config

On Seastone2:

serdes_lane_config_dfe=on; not read by the SDK on that switch

serdes_lcpll
Type:
number
Default:
0

Serdes reference clock selection External Clock = 0, Internal LCPLL = 1

serdes_preemphasis
Type:
number

Transmit equaliser (FIR taps) of a port: 0x<post><main><pre>, one byte each (bits 0–7 pre-cursor, 8–15 main, 16–23 post-cursor). serdes_preemphasis_<port> sets all lanes of the port; serdes_preemphasis_lane<L>_<port> sets lane L and takes precedence. Values depend on the board and the cable or optic; copy them from the vendor’s file.

Forms:

serdes_preemphasis_lane<N>_<port>, serdes_preemphasis_<port>, serdes_preemphasis

SONiC:

set in 9 Trident 3 HWSKU files; 0x105004, 0x164105, 0x14410a

On Seastone2:

serdes_preemphasis_91=0x0f4d08, serdes_preemphasis_83=0x0d4f08, serdes_preemphasis_75=0x0d4f08, serdes_preemphasis_67=0x0d4f08 and 28 more

serdes_rx_los
Type:
number

Enable serdes Loss Of Signal(LOS) function. 0 disable, 1 enable

Forms:

serdes_rx_los_<port>, serdes_rx_los_<type>, serdes_rx_los

serdes_rx_los_invert
Type:
number

Invert serdes LOS signal level. 0 not invert, 1 invert

Forms:

serdes_rx_los_invert_<port>, serdes_rx_los_invert_<type>, serdes_rx_los_invert

serdes_scrambler_enable
Type:
number

Serdes scrambler enable

Forms:

serdes_scrambler_enable_<port>, serdes_scrambler_enable_<type>, serdes_scrambler_enable

serdes_timesync_adjust_in_linkscan
Type:
number
Forms:

serdes_timesync_adjust_in_linkscan_<port>, serdes_timesync_adjust_in_linkscan_<type>, serdes_timesync_adjust_in_linkscan

serdes_timesync_enable
Type:
number
Default:
0

This configuration property is used to enable/disable Serdes PHY TimeSync. This property may be configured with the base name to control all ports, or with the suffix “_lport#” to configure a specific port. This is only for Tomahawk3.

Forms:

serdes_timesync_enable_<port>, serdes_timesync_enable_<type>, serdes_timesync_enable

serdes_timesync_one_step_enable
Type:
number
Default:
0

This configuration property is used to enable One Step Serdes PHY TimeSync One step is diabled or not specifiy, two step will be enabled. This property may be configured with the base name to control all ports, or with the suffix “_lport#” to configure a specific port. This is only for Tomahawk3.

Forms:

serdes_timesync_one_step_enable_<port>, serdes_timesync_one_step_enable_<type>, serdes_timesync_one_step_enable

serdes_tx_los_usec
Type:
number

TX serdes LOS interval to reset the LP receiver

serdes_tx_taps
Type:
string

Transmit equaliser as a list, serdes_tx_taps_<port>=nrz:<pre>:<main>:<post>:…; overrides serdes_preemphasis when set.

Forms:

serdes_tx_taps_<port>, serdes_tx_taps_<type>, serdes_tx_taps

sw_autoneg_polling_interval
Type:
number

Software Autoneg Polling Interval in msec

xphy_primary_core_num
Type:
number

This specifies the primary core number to which it belongs to.

Forms:

xphy_primary_core_num_<port>, xphy_primary_core_num_<type>, xphy_primary_core_num