`DPLL`

DPLL operations on SPI bus

Read or write a register of a DPLL (clock synchronisation chip) on the switch chip’s master SPI bus:

dpll [Config=<n>] [<options>] write <addr> <data>
dpll [Config=<n>] [<options>] read <addr>

read prints the byte in hex. Options default to the dpll_params configuration property; Config=<n> selects a preset. The options are DevSel, CPOL, CPHA, AddrBitOrder, DataBitOrder, AddrWidth, UseBrstBit and UseRwBit, each Name=<value>.

Warning

dpll write changes the timing chip of a board that has one (used for SyncE/1588). Do not use on a production switch.

The built-in help writes one option as UseBrstBit-0/1; it is set like the others, UseBrstBit=<0|1>.

Unvalidated

drivshell> dpll read <addr>

Built-in help

dpll [Config = n] [<Options>] write <addr> <data>
    dpll [Config = n] [<Options>] read <addr>
    "Config" overrides all the options with preset values
    Takes default <options> from "dpll_params" config variable if present
    Options are the following, separated by space:
      DevSel=n : Override Mux for DPLL Selection
      CPOL=0/1 : Clock Polarity
      CPHA=0/1 : Clock Phase
      AddrBitOrder=0/1 : 0 = MSB..LSB, 1 = LSB..MSB
      DataBitOrder=0/1 : 0 = MSB..LSB, 1 = LSB..MSB
      AddrWidth=1/2 : No of Bytes used for Addr
      UseBrstBit-0/1 : Reserve Bit-0 of Addr as Burst Bit
      UseRwBit=0/1 : Use MSBit (Bit-15 / Bit-7) of Addr as R/W' Bit

DPLL

`DPLL`