`Getreg`

Get register

Getreg

Shortest form: g.

Read registers and print them with their fields decoded. A register can be given by name, by name with a port or index (CLMAC_CTRL.ce0, PROTOCOL_PKT_CONTROL[0]), or by address; see Memories and registers. Read-only, but reading a clear-on-read register (some counters and status registers) clears it.

Grammar:

getreg [raw] [hex] [chg] [<REGTYPE>] <REGISTER> [<FIELD> ...]

raw, hex and chg must be typed in full (any case). <REGTYPE> defaults to SOC (internal registers); PCIM reads CMIC registers by name or offset, and the other types (PCIC, IPROC, PHY, MW …) take an address. Field names after the register limit the output to those fields. Each register instance is printed as <NAME>.<block>[<instance>][<address>]=<value>: <FIELD=value,...>, for example RDBGC0_SELECT.ipipe0[1][0x86003d00]=0x800: <BITMAP=0x800>.

A name that is unknown, or not valid on this chip, prints Syntax error parsing "<name>" and the command fails. Not every register name from other Broadcom chips exists on a Trident 3: CMIC_DEV_REV_ID, for one, is rejected.

Hardware-validated

drivshell> getreg ING_CONFIG_64
ING_CONFIG_64.ipipe0[1][0x4e018000]=0x1fe08001c0007: <VFP_PRI_ACTION_FB2_MODE=0,
   USE_PROT_STATUS=0,USE_PPD_SOURCE=0,TUNNEL_URPF_MODE=0,TUNNEL_URPF_DEFAULTROUTECHECK=0,
   SVL_ENABLE=0,STNMOVE_ON_L2SRC_DISC=0,PARSER_2_DEFAULT_IPV4_OPTIONS_HDR_CHECKSUM_CONTROL=0,
   PARSER_1_DEFAULT_IPV4_OPTIONS_HDR_CHECKSUM_CONTROL=0,NAT_ENABLE=0,
   MY_STATION_CLASSID_SELECT=0,MLD_PKTS_UNICAST_IGNORE=0,MLD_CHECKS_ENABLE=0,
   LOOKUP_L2MC_WITH_FID_ID=0,LBID_RTAG=0,L3SRC_HIT_ENABLE=1,L3IIF_URPF_SELECT=0,
   L2_ENTRY_USED_AS_MY_STATION=0,L2MC_LOOKUP_USE_BROADCAST_DOMAIN=0,
   L2DST_HIT_ENABLE=0,IPV6_RESERVED_MC_ADDR_MLD_ENABLE=0,IPV6_MC_MACDA_CHECK_ENABLE=0,
   IPV4_RESERVED_MC_ADDR_IGMP_ENABLE=0,IPV4_MC_MACDA_CHECK_ENABLE=0,
   IPHDR_ERROR_L3_LOOKUP_ENABLE=1,IGNORE_PPD2_PRESERVE_QOS=0,IGNORE_PPD0_PRESERVE_QOS=0,
   IGNORE_MY_MODID=0,IGNORE_HG_HDR_LAG_FAILOVER=0,IGNORE_HG_HDR_HDR_EXT_LEN=0,
   IGNORE_HG_HDR_DONOT_LEARN=0,IGMP_PKTS_UNICAST_IGNORE=0,HIGIG2_ECN_IN_CC_ENABLE=0,
   ENABLE_L3_CLASSID_FOR_L2PKTS=0,ARP_VALIDATION_EN=1,ARP_RARP_TO_FP=3,
   APPLY_MTU_CHECK_ON_HIGIG_IPMC=0,APPLY_HG_MGID_ADJUST=0xff,APPLY_EGR_MASK_ON_L3=1,
   APPLY_EGR_MASK_ON_L2=1>

Hardware-validated — One port’s MAC control register, two fields only

drivshell> getreg CLMAC_CTRL.ce0 RX_EN TX_EN
CLMAC_CTRL.ce0[15][0x60000]=0xd040: <TX_EN=0,RX_EN=0>

Getreg chg <REGISTER>

Print only the fields, and for multi-instance registers only the instances, whose value differs from the reset default. A quick way to see what the SDK configured.

Hardware-validated

drivshell> getreg chg TOP_PVTMON_RESULT_0
TOP_PVTMON_RESULT_0.top0[7][0x2004700]=0x2d62de: <PVT_DATA=0x2de,
   MIN_PVT_DATA=0x2d6>

Getreg raw <REGISTER>

Print the value without decoding fields. hex prints only the hex value, for scripts. The flags can be combined.

Hardware-validated

drivshell> getreg raw RDBGC0_SELECT
RDBGC0_SELECT.ipipe0[1][0x86003d00]=0x800

Getreg PCIM <cmic_register>

Read a CMIC register through the PCI memory window, by name (with or without the CMIC_ prefix) or by offset. An offset with no register name behind it is printed as cpu[(nil)] = <value>, without a name or field decode.

Hardware-validated

drivshell> getreg pcim 0x0
cpu[(nil)] = 0x5000

Built-in help

Parameters: [hex|raw|chg] [<REGTYPE>] <REGISTER> [[field1]..[fieldN]]
    If <REGTYPE> is not specified, it defaults to "soc".
    <REGISTER> designates offset, address, or symbolic name.
    If hex is specified, dumps only a hex value (for Expect parsing).
    If raw is specified, no field decoding is done.
    If chg is specified, show only fields/regs changed from defaults.
    For a list of register types, use "dump".