`PCIEPHY`

PCIe PHY speicific utilities

PCIEPHY

Access the PCIe SerDes (PHY) and PCIe core of the switch ASIC, and manage the PCIe firmware stored in the ASIC’s QSPI flash. Sub-command keywords must be typed in full (any case).

Warning

pciephy setreg, setepreg, modepreg and the fw access write form change the PCIe link that connects the ASIC to the CPU. A wrong value can drop the link, which takes syncd down with it. pciephy fw load reprograms the flash; the new firmware only runs after a reboot, and a bad image can leave the switch unable to bring up PCIe.

The built-in help starts the grammar with an optional <cores group> number. This shell does not accept one: a leading number is answered with Command NOT supported.

Hardware-validated

drivshell> pciephy fw version
     PCIe FW loader version: 2.5
     PCIe FW version: D102_08

pciephy fw version

Show the PCIe firmware loader version and the SerDes firmware version stored in flash (PCIe FW loader version: <a>.<b> and PCIe FW version: <string>). Read-only. If the flash cannot be read it prints Error: Init SPI flash speed = <hz>, mode =<n> and fails.

Hardware-validated

drivshell> pciephy fw version
  PCIe FW loader version: 2.5
  PCIe FW version: D102_08

pciephy fw info [raw]

Show information about the PCIe firmware loader; raw adds the firmware’s trace log. Read-only. On a SONiC Trident 3 switch pciephy fw info prints the same two version lines as pciephy fw version and nothing more.

Hardware-validated

drivshell> pciephy fw info
  PCIe FW loader version: 2.5
  PCIe FW version: D102_08

pciephy fw load <file>

Write a PCIe firmware image from a file in the syncd container to the QSPI flash and verify it. Prints the image size, Updating PCIE firmware, and PCIE firmware updated successfully. Please reset the system.... pciephy fw cmp <file> only compares flash with the file.

Unvalidated

drivshell> pciephy fw cmp <file>

pciephy fw access <pcie | i2c_bde | i2c <bus> <device> | read <axi_address> | write <axi_address> <value>>

Choose how the firmware commands reach the flash (pcie is the default), or read/write four bytes at an AXI address with the chosen method. Also reachable as pciephy access ….

Unvalidated

drivshell> pciephy fw access pcie

pciephy fw timer_test <register> <seconds>

Measure a CMIC/iProc timer register against the system clock for the given number of seconds and print the nanoseconds per tick. Blocks the shell for that time.

Unvalidated

drivshell> pciephy fw timer_test <register> 1

pciephy getreg <phy_address>

Read a PCIe SerDes register and print address: 0x…, data = 0x…. pciephy setreg <phy_address> <value> writes one.

Unvalidated

drivshell> pciephy getreg 0xd230

pciephy getepreg <core_address>

Read a PCIe core (endpoint) configuration register through the indirect PAXB_0_CONFIG_IND window. setepreg <core_address> <value> writes one. modepreg <core_address> <data> <mask> <shift> is a read-modify-write of a bit field that the built-in help does not mention.

Unvalidated

drivshell> pciephy getepreg 0xbc

pciephy pramread <offset> <words>

Read 16-bit words from the PCIe PHY’s program RAM.

Unvalidated

drivshell> pciephy pramread 0x0 0x20

pciephy diag <lanes> <dsc | state | eyescan>

SerDes lane diagnostics: dsc core and lane state, state adds all lanes and the event log, eyescan an eye scan of the selected lane. <lanes> is a lane bitmap such as 0x1. An eye scan disturbs the lane while it runs.

Unvalidated

drivshell> pciephy diag 0x1 dsc

Built-in help

Usages:
    Parameters: [<cores group>] <sub_cmd> [sub cmd parameters]
    <cores group> - cores group number for a composite device, if not specified the command is excecuted on all cores groups
    The list of sub commands:
       getreg - displays value of given phy register
              Syntax: pciephy getreg <PHY register address>
              Example:
                BCM.0> pciephy getreg 0xd230
       setreg - writes given value into given phy register
              Syntax: pciephy setreg <PHY register address> <value>
              Example:
                BCM.0> pciephy setreg 0xd230 0xa555
       getepreg - displays value of given pcie core(endpoint) register
              Syntax: pciephy getepreg <pcie core register address>
              Example:
                BCM.0> pciephy getepreg 0xbc
       setepreg - writes given value into given pcie core(endpoint) register
              Syntax: pciephy setepreg <pcie core register address> <value>
              Example:
                BCM.0> pciephy setepreg 0xbc 0x12345678
       pramread - Reads and displays pcie phy pram content at given address
              Syntax: pciephy pramread <pram address offset> <number of 16-bit words to read>
              Example:
                BCM.0> pciephy pramread 0x0 0x20
       diag - display SerDes lane information.
              Syntax: pciephy diag <lane bit map> <diag sub-command>
              Example:
                BCM.0> pciephy diag 0x1 dsc
                BCM.0> pciephy diag 0x1 state
                BCM.0> pciephy diag 0x1 eyescan
              diag - sub commands:
                dsc - Display core state and lane state
                state - Discplay core state, lane state for all lanes and event log
                eyescan - Display eyescan for selected lane
       fw - Load SerDes(PCIe Gen3) firmware, display firmware version
            Syntax: pciephy fw <fw sub-command> [fw sub cmd parameters]
            Example:
              BCM.0> pciephy fw load <firmware file>
            fw - sub commands:
              load <file> - programs contents of given firmware file to QSPI flash
              cmp <file> - Compare flash content with given file
              version - displays PCIe fw loader and SerDes fw versions
              info [raw] - displays PCIe fw loader running status
              access - sets the method used to access the firmware or tests it.  sub commands:
                pcie - (default) Use the device's PCIe connection for access
                i2c_bde - Use the device's BDE I2C functions for access
                i2c <I2C bus number> <slave device ID> - Use I2C using the give bus and device IDs
                read <AXI address> - read four bytes using the current access method
                write <AXI address> <value> - write four bytes using the current access method
              timer_test <CMIC/IPROC register> <Number of seconds to test> - test the timer by giving the IPROC register as an imput and a time to measure in seconds.